X5648 INTERSIL [Intersil Corporation], X5648 Datasheet - Page 5

• Manufacturer Part Number: X5648
• Description: CPU Supervisor with 64Kbit SPI EEPROM
• Manufacturer: INTERSIL [Intersil Corporation]

Figure 4. Sample V
SPI SERIAL MEMORY
The memory portion of the device is a CMOS serial
EEPROM array with Intersil’s block lock protection. The
array is internally organized as x 8. The device features
a Serial Peripheral Interface (SPI) and software proto-
col allowing operation on a simple four-wire bus.
The device utilizes Intersil’s proprietary Direct Write
cell, providing a minimum endurance of 100,000
cycles and a minimum data retention of 100 years.
The device is designed to interface directly with the
synchronous Serial Peripheral Interface (SPI) of many
popular micro controller families. It contains an 8-bit
instruction register that is accessed via the SI input,
with data being clocked in on the rising edge of SCK.
CS must be LOW during the entire operation.
All instructions (Table 1), addresses and data are trans-
ferred MSB first. Data input on the SI line is latched on
the first rising edge of SCK after CS goes LOW. Data is
output on the SO line by the falling edge of SCK. SCK is
static, allowing the user to stop the clock and then start
it again to resume operations where left off.
Table 1. Instruction Set
Note:
Instruction Name
WRDI/RFLB
V
*Instructions are shown MSB in left most position. Instructions are transferred MSB first.
Adj.
TRIP
WRITE
WREN
WRSR
RSDR
READ
SFLB
Program
TRIP
Instruction Format*
Reset Circuit
5
0000 0110
0000 0000
0000 0100
0000 0101
0000 0001
0000 0011
0000 0010
4.7K
+
NC
Set the write enable latch (enable write operations)
Reset the write enable latch/reset flag bit
Read status register
Write status register (watchdog, block lock, WPEN & flag bits)
Read data from memory array beginning at selected address
Write data to memory array beginning at selected address
Set flag bit
X5648, X5649
™
1
2
3
4
X5648/49
8
7
6
5
Write Enable Latch
The device contains a write enable latch. This latch
must be SET before a write operation is initiated. The
WREN instruction will set the latch and the WRDI
instruction will reset the latch (Figure 3). This latch is
automatically reset upon a power-up condition and
after the completion of a valid write cycle.
Status Register
The RDSR instruction provides access to the status
register. The status register may be read at any time,
even during a write cycle. The status register is for-
matted as follows:
The Write-In-Progress (WIP) bit is a volatile, read only
bit and indicates whether the device is busy with an
internal nonvolatile write operation. The WIP bit is read
using the RDSR instruction. When set to a “1”, a non-
volatile write operation is in progress. When set to a
“0”, no write is in progress.
10K
WPEN
7
FLB
10K
6
Operation
5
0
NC
NC
4
0
4.7K
BL1
3
RESET
Reset V
Test V
Set V
BL0
2
TRIP
TRIP
TRIP
WEL WIP
V
1
March 17, 2005
P
FN8136.0
0