AK5701VN AKM [Asahi Kasei Microsystems], AK5701VN Datasheet - Page 37

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AK5701VN

Manufacturer Part Number
AK5701VN
Description
PLL & MIC-AMP 16-Bit Stereo ADC
Manufacturer
AKM [Asahi Kasei Microsystems]
Datasheet

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ASAHI KASEI
3. ALC動作設定手順例
Table 28は、録音パスの場合のALC設定例です。
ALC動作中は、 以下のビットへの変更を禁止します。 これらのビットを変更する場合は、 ALC動作を終了(ALC
bit = “0”またはPMADL = PMADR bits = “0”)してから行って下さい。
MS0404-J-00
Register Name
LMTH
ZELMN
ZTM1-0
WTM1-0
REF7-0
IVL7-0,
IVR7-0
LMAT1-0
RGAIN1-0
ALC
・LMTH, LMAT1-0, WTM1-0, ZTM1-0, RGAIN1-0, REF7-0, ZELMNの各ビット
WR (LMAT1-0, RGAIN1-0, ZELMN, LMTH1-0; ALC= “1”)
Maximum gain at recovery operation
Limiter ATT step
Recovery GAIN step
WR (ZTM1-0, WTM1-0)
Comment
Limiter detection Level
Limiter zero crossing detection
Zero crossing timeout period
Recovery waiting period
*WTM1-0 bits should be the same data
Gain of IVOL
ALC enable
as ZTM1-0 bits
Note : WR : Write
WR (IVL/R7-0)
ALC Operation
Manual Mode
WR (REF7-0)
* The value of IVOL should be
Figure 39. ALC動作設定手順例
the same or smaller than REF’s
Table 28. ALC設定例
- 37 -
Data
E1H
91H
01
00
00
00
00
0
1
fs=8kHz
Example:
Operation
−4.1dBFS
Enable
+30dB
Enable
1 step
1 step
16ms
16ms
0dB
Limiter = Zero crossing Enable
Recovery Cycle = 16ms@8kHz
Limiter and Recovery Step = 1
Maximum Gain = +30.0dB
Limiter Detection Level = −4.1dBFS
ALC bit = “1”
(3) Addr=1BH, Data=E1H
(1) Addr=18H&19H, Data=91H
(2) Addr=1AH, Data=00H
(4) Addr=1CH, Data=81H
Data
E1H
91H
01
10
10
00
00
0
1
fs=44.1kHz
Operation
−4.1dBFS
11.6ms
11.6ms
Enable
Enable
+30dB
1 step
1 step
0dB
[AK5701]
2005/08

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