PN5110A0HN NXP [NXP Semiconductors], PN5110A0HN Datasheet - Page 9

• Manufacturer Part Number: PN5110A0HN
• Description: Transmission Module
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
Table 4.
082733
Product short data sheet
Symbol
A2 to A5
PVDD
DVDD
DVSS
PVSS
NRSTPD
SIGIN
SIGOUT
LOADMOD
TVSS
TX1
TVDD
TX2
TVSS
AVDD
VMID
RX
AVSS
AUX1
AUX2
OSCIN
OSCOUT
IRQ
NWR
NRD
ALE
NCS
D0 to D7
A0 to1 A1
Pin description HVQFN40
Pin
1 to 4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 to 38
39 to 40
Type
I
PWR
PWR
PWR
PWR
I
I
O
O
PWR
O
PWR
O
PWR
PWR
PWR
I
PWR
O
O
I
O
O
I
I
I
I
I/O
I
Description
Address Line
Pad power supply
Digital Power Supply
Digital Ground
Pad power supply ground
Not Reset and Power Down: When LOW, internal current sinks are switched off, the
oscillator is inhibited, and the input pads are disconnected from the outside world. With
a positive edge on this pin the internal reset phase starts.
Communication Interface Input: accepts a digital, serial data stream
Communication Interface Output: delivers a serial data stream
Load Modulation Output: provides digital signal for FeliCa and Mifare Card Operation
mode
Transmitter Ground: supplies the output stage of TX1 and TX2
Transmitter 1: delivers the modulated 13.56 MHz energy carrier
Transmitter Power Supply: supplies the output stage of TX1 and TX2
Transmitter 2: delivers the modulated 13.56 MHz energy carrier
Transmitter Ground: supplies the output stage of TX1 and TX2
Analog Power Supply
Internal Reference Voltage: This pin delivers the internal reference voltage.
Receiver Input
Analog Ground
Auxiliary Outputs: These pins are used for testing.
Crystal Oscillator Input: input to the inverting amplifier of the oscillator. This pin is
also the input for an externally generated clock (f
Crystal Oscillator Output: Output of the inverting amplifier of the oscillator.
Interrupt Request: output to signal an interrupt event
Not Write: strobe to write data (applied on D0 to D7) into the PN511 register
Not Read: strobe to read data from the PN511 register (applied on D0 to D7)
Address Latch Enable: signal to latch AD0 to AD5 into the internal address latch
when HIGH.
Not Chip Select: selects and activates the host controller interface of the PN511
8-bit Bi-directional Data Bus.
Remark: For serial interfaces this pins can be used for test signals or I/Os.
Remark: If the host controller selects I
can be used to define the I
Address Line
Rev. 3.3 — 13 June 2007
2
C address.
2
C as digital host controller interface, these pins
osc
= 27.12 MHz).
Transmission Module
© NXP B.V. 2007. All rights reserved.
PN511
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