AM79C976 Advanced Micro Devices, AM79C976 Datasheet

AM79C976

Manufacturer Part Number

AM79C976

Description

PCnet-PRO 10/100 Mbps PCI Ethernet Controller

Manufacturer

Advanced Micro Devices

Datasheet

1.AM79C976.pdf (309 pages)

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Am79C976

PCnet-PRO™

10/100 Mbps PCI Ethernet Controller

DISTINCTIVE CHARACTERISTICS

This document contains information on a product under development at Advanced Micro Devices. The information

is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed

product without notice.

Integrated Fast Ethernet controller for the

Peripheral Component Interconnect (PCI) bus

— 32-bit glueless PCI host interface

— Supports PCI clock frequency from DC to

— Supports network operation with PCI clock

— High performance bus mastering

— PCI specification revision 2.2 compliant

— Supports PCI Subsystem/Subvendor

— Supports both PCI 3.3-V and 5.0-V signaling

— Plug and Play compatible

— Uses advanced PCI commands (MWI, MRL,

— Optionally supports PCI bursts aligned to

— Supports big endian and little endian byte

— Implements optional PCI power management

— Supports 40-bit addressing (using PCI Dual

Media Independent Interface (MII) for

connecting external 10/100 megabit per second

(Mbps) transceivers

— IEEE 802.3-compliant MII

— Intelligent Auto-Poll™ external PHY status

— Supports both auto-negotiable and non auto-

— Supports 10BASE-T, 100BASE-TX/FX,

33 MHz independent of network clock

from 15 MHz to 33 MHz

architecture with integrated Direct Memory

Access (DMA) Buffer Management Unit for

low CPU and bus utilization

ID/Vendor ID programming through the

EEPROM interface

environments

MRM)

cache line boundaries

alignments

event (PME) pin

Address Cycles)

monitor and interrupt

negotiable external PHYs

100BASE-T4, and 100BASE-T2 IEEE 802.3-

compliant MII PHYs at full- or half-duplex

PRELIMINARY

Refer to AMD’s Website (www.amd.com) for the latest information.

Full-duplex operation supported with

independent Transmit (TX) and Receive (RX)

channels

Includes support for IEEE 802.1Q VLANs

— Automatically inserts, deletes, or modifies

— Optionally filters untagged frames

Provides optional flow control features

— Recognizes and transmits IEEE 802.3x MAC

— Asserts collision-based back pressure in

Provides internal Management Information

Base (MIB) counters for network statistics

Supports PC97, PC98, PC99, and Net PC

requirements

— Implements full OnNow features including

— Implements Magic Packet™ mode

— Magic Packet mode and the physical address

— Supports PCI Bus Power Management

— Supports Advanced Configuration and

— Supports Network Device Class Power

Large independent external TX and RX FIFOs

— Supports up to 4 megabytes (Mbytes)

— Programmable FIFO watermarks for both

— Receive frame queuing for high latency PCI

— Programmable allocation of buffer space

VLAN tag

flow control frames

half-duplex mode

pattern matching and link status wake-up

loaded from EEPROM at power up without

requiring PCI clock

Interface Specification Version 1.1

Power Interface (ACPI) Specification Version

1.0

Management Specification Version 1.0

external SSRAM for RX and TX frame storage

transmit and receive operations

bus host operation

between transmit and receive queues

Publication# 22929

Issue Date: August 2000

Rev: C Amendment/0

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