AM79C976 Advanced Micro Devices, AM79C976 Datasheet - Page 155

• Manufacturer Part Number: AM79C976
• Description: PCnet-PRO 10/100 Mbps PCI Ethernet Controller
• Manufacturer: Advanced Micro Devices

INTEN0: Interrupt0 Enable
Offset 040h
This register allows the software to specify which types
of interrupt events will cause the INTR bit in the
Interrupt0 register to be set, which in turn will cause
INTA pin to be asserted if the INTREN bit in CMD0 is
set. Each bit in this register corresponds to a bit in the
Interrupt0 register. Setting a bit in this register enables
the corresponding bit in the Interrupt0 register to cause
the INTR bit to be set.
8/01/00
30-28
Bit
31
27
26
25
24
23
22
21
20
19
18
17
16
15
14
MIIPDTINTEN
SPNDINTEN
MCCIINTEN
MCCINTEN
MREINTEN
APINT5EN
APINT4EN
APINT3EN
APINT2EN
APINT1EN
APINT0EN
LCINTEN
Name
VAL3
VAL2
VAL1
RES
Value bit for byte 3. The value of this bit is written to any bits in the INTEN0 register that correspond
to bits in the INTEN0[30:24] bit map field that are set to 1.
Reserved locations. Written as zeros and read as undefined.
Link Change Interrupt Enable. When this bit is set, the INTR bit will be set when the LCINT bit in
INT0 is set.
Auto-Poll Interrupt from Register 5 Enable. When this bit is set, the INTR bit will be set when the
APINT5 bit in INT0 is set.
Auto-Poll Interrupt from Register 4 Enable. When this bit is set, the INTR bit will be set when the
APINT4 bit in INT0 is set.
Auto-Poll Interrupt from Register 3 Enable. When this bit is set, the INTR bit will be set when the
APINT3 bit in INT0 is set.
Value bit for byte 2. The value of this bit is written to any bits in the INTEN0 register that correspond
to bits in the INTEN0[22:16] bit map field that are set to 1.
Auto-Poll Interrupt from Register 2 Enable. When this bit is set, the INTR bit will be set when the
APINT2 bit in INT0 is set.
Auto-Poll Interrupt from Register 1 Enable. When this bit is set, the INTR bit will be set when the
APINT1 bit in INT0 is set.
Auto-Poll Interrupt from Register 0 Enable. When this bit is set, the INTR bit will be set when the
APINT0 bit in INT0 is set.
MII PHY Detect Transition Interrupt Enable. When this bit is set, the INTR bit will be set when the
MIIPDTINT bit in INT0 is set.
This bit is an alias of CSR7, bit 0.
MII Management Command Complete Internal Interrupt Enable. When this bit is set, the INTR bit
will be set when the MCCIINT bit in INT0 is set.
This bit is an alias of CSR7, bit 2.
MII Management Command Complete Interrupt Enable. When this bit is set, the INTR bit will be
set when the MCCINT bit in INT0 is set.
This bit is an alias of CSR7, bit 4.
MII Management Read Error Interrupt Enable. When this bit is set, the INTR bit will be set when
the MREINT bit in INT0 is set.
This bit is an alias of CSR7, bit 8
Value bit for byte 1. The value of this bit is written to any bits in the INTEN0 register that correspond
to bits in the INTEN0[14:8] bit map field that are set to 1.
Suspend Interrupt Enable. When this bit is set, the INTR bit will be set when the SPNDINT bit in
INT0 is set.
Table 60.
P R E L I M I N A R Y
INTEN0: Interrupt0 Enable Register
Am79C976
INTEN0 is a command style register. The high order bit
of each byte of this register is a ’value’ bit that specifies
the value that will be written to selected bits of the reg-
ister. The seven low order bits of each byte make up a
bit map that selects which register bits will be altered.
All bits in this register are cleared to 0 by H_RESET. All
bits are also cleared before EEPROM data are loaded
or after an EEPROM read failure.
The RINTEN and TINTEN bits are set after S_RESET
(but not H_RESET).
Description
155