AM79C976 Advanced Micro Devices, AM79C976 Datasheet - Page 131

• Manufacturer Part Number: AM79C976
• Description: PCnet-PRO 10/100 Mbps PCI Ethernet Controller
• Manufacturer: Advanced Micro Devices

Offset 050h
8/01/00
Bit
Bit
31
30
3
2
1
0
RX_SPND
TX_SPND
NOUFLO
INTREN
Name
Name
VAL3
RUN
Value bit for byte 3. The value of this bit is written to any bits in the CMD2 register that correspond
to bits in the CMD2[30:24] bit map field that are set to 1.
No Underflow on Transmit. When the NOUFLO bit is set to 1, the Am79C976 controller will not start
transmitting the preamble for a packet until the Transmit Start Point (CTRL1, bits 16-17)
requirement has been met and the complete packet has been copied into the transmit FIFO. When
the NOUFLO bit is cleared to 0, the Transmit Start Point is the only restriction on when preamble
transmission begins for transmit packets.
Setting the NOUFLO bit guarantees that the Am79C976 controller will never suffer transmit
underflows, because the arbiter that controls transfers to and from the SSRAM guarantees a worst
case latency on transfers to and from the MAC and Bus Transmit FIFOs such that it will never
underflow if the complete packet has been copied into the Am79C976 controller before packet
transmission begins.
This bit is an alias of BCR18, bit 11. It is included only to allow programming from the EEPROM for
compatibility with legacy software.
Receive Suspend. Setting this bit causes the receiver to suspend its activities without stopping in
the middle of a frame reception. After the receiver suspends its activities, the DMA controller
continues copying data from the Receive FIFO into host system memory until the FIFO is empty
or until no more receive descriptors are available.
After the Receive FIFO has been emptied or after all receive descriptors have been used, the
receive DMA controller suspends its polling activity, and the RX_SUSPENDED bit in the Status
register and the Suspend Interrupt (SPNDINT) bit in the Interrupt register will be set. Setting the
SPNDINT bit will cause an interrupt to occur if interrupts are enabled and the SPNDINTEN bit in
the Interrupt Enable register is set.
Transmit Suspend. Setting this bit causes the transmitter to suspend its activities without stopping
in the middle of a frame transmission. After the transmitter suspends its activities, the DMA
controller continues copying data from host system memory into the Transmit FIFO until the FIFO
is full or until no more transmit descriptors are available.
After the Transmit FIFO has been filled or after all transmit descriptors have been used, the
transmit DMA controller suspends its polling activity, and the TX_SUSPENDED bit in the Status
register and the Suspend Interrupt (SPNDINT) bit in the Interrupt register will be set. Setting the
SPNDINT bit will cause an interrupt to occur if interrupts are enabled and the SPNDINTEN bit in
the Interrupt Enable register is set.
Interrupt Enable. This bit allows INTA to be asserted if any bit in the Interrupt register is set. If
INTREN is cleared to 0, INTA will not be asserted, regardless of the state of the Interrupt register.
INTREN is not an alias of the IENA bit in CSR0.
Setting the RUN bit enables the Am79C976 controller to start processing descriptors and
transmitting and receiving packets.
Clearing the RUN bit to 0 abruptly disables the transmitter, receiver, and descriptor processing
logic, possibly while a frame is being transmitted or received.
The act of changing the RUN bit from 1 to 0 causes the following bits to be reset to 0: IENA,
TX_SPND, RX_SPND, TDMD, RDMD, UINTCMD, TX_FAST_SPND, RINT, TINT, TXSTRTINT,
TXDNINT, MPINT, and UINT.
Table 43.
P R E L I M I N A R Y
CMD2: Command2 Register
Am79C976
CMD2 is a command-style register. All bits in this reg-
ister are cleared to 0 when the RST pin is asserted, be-
fore the serial EEPROM is read, and after a serial
EEPROM read error.
Description
Description
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