AM79C976 Advanced Micro Devices, AM79C976 Datasheet - Page 182

• Manufacturer Part Number: AM79C976
• Description: PCnet-PRO 10/100 Mbps PCI Ethernet Controller
• Manufacturer: Advanced Micro Devices

12
11
10
182
CHDPOLL
STINT
STINTE
when it fetches a receive De-
scriptor. RDMD is cleared by
H_RESET
RDMD is unaffected by setting
the STOP bit.
POLL is set, the Buffer Manage-
ment Unit will disable chain
polling. Likewise, if CHDPOLL is
cleared, automatic chain polling
is enabled.
the Buffer Management Unit is in the
middle of a buffer-changing opera-
tion, setting the RDMD bit in CMD0 or
CSR7 will cause a poll of the current
receive descriptor, and setting the
TDMD bit in CMD0 or CRR0 will
cause a poll of the current transmit
descriptor.
RDMD bit in CSR7 can be set to
initiate a manual poll of a receive
or transmit descriptor if the Buffer
Management Unit is in the middle
of a buffer-chaining operation.
Read/Write
POLL is cleared by H_RESET.
CHDPOLL
S_RESET or by setting the STOP
bit.
Software Timer interrupt is set by
the Am79C976 controller when
the Software Timer counts down
to 0. The Software Timer will im-
mediately load the STVAL (BCR
31, bits 5-0) into the Software
Timer and begin counting down.
When STINT is set to 1, INTA is
asserted if the enable bit STINTE
is set to 1.
Read/Write accessible. STINT is
cleared by the host by writing a 1.
Writing a 0 has no effect. STINT
is cleared by H_RESET and is
not affected by S_RESET or set-
ting the STOP bit.
If STINTE is set, the STINT bit
will be able to set the INTR bit.
Read/Write accessible. STINTE
is set to 0 by H_RESET and is not
Disable Chain Polling. If CHD-
Software Timer Interrupt. The
Software Timer Interrupt Enable.
If CHDPOLL is set, the
If CHDPOLL is set and
or
is
accessible.
by
unaffected
P R E L I M I N A R Y
S_RESET.
CHD-
Am79C976
by
9
8
7
MREINT
MREINTE
MAPINT
affected by S_RESET or setting
the STOP bit.
When MREINT is set to 1, INTA is
asserted if the enable bit MREIN-
TE is set to 1.
Read/Write accessible. MREINT
is cleared by the host by writing a
1. Writing a 0 has no effect. MRE-
INT is cleared by H_RESET and
is not affected by S_RESET or
setting the STOP bit.
Read/Write accessible. MREIN-
TE is set to 0 by H_RESET and is
not affected by S_RESET or set-
ting the STOP bit
When MAPINT is set to 1, INTA is
asserted if the enable bit MAP-
INTE is set to 1.
Read/Write accessible. MAPINT
is cleared by the host by writing a
1. Writing a 0 has no effect. MAP-
INT is cleared by H_RESET and
MII Management Read Error In-
terrupt. The MII Read Error inter-
rupt is set by the Am79C976
controller to indicate that the cur-
rently read register from the ex-
ternal
contents of BCR34 are incorrect
and that the operation should be
performed again. The indication
of an incorrect read comes from
the PHY. During the read turn-
around time of the MII manage-
ment frame the external PHY
should drive the MDIO pin to a
LOW state. If this does not hap-
pen, it indicates that the PHY and
the Am79C976 controller have
lost synchronization.
MII Management Read Error In-
terrupt Enable. If MREINTE is
set, the MREINT bit will be able to
set the INTR bit.
rupt. This bit is set when the
Auto-Poll State Machine detects
a change in any PHY register that
is polled by the Auto-Poll State
Machine.
MII Management Auto-Poll Inter-
PHY
is
invalid.
8/01/00
The