AM79C976 Advanced Micro Devices, AM79C976 Datasheet - Page 156

• Manufacturer Part Number: AM79C976
• Description: PCnet-PRO 10/100 Mbps PCI Ethernet Controller
• Manufacturer: Advanced Micro Devices

156
11-9
Bit
3-1
13
12
8
7
6
5
4
0
TXSTRTINTEN
TXDNINTEN
MPINTEN
STINTEN
RINTEN
SINTEN
TINTEN
Name
VAL1
RES
RES
Magic Packet Interrupt Enable. When this bit is set, the INTR bit will be set when the MPINT bit in
INT0 is set.
This bit is an alias of CSR5, bit 3.
System Interrupt Enable. When this bit is set, the INTR bit will be set when the SINT bit in INT0 is
set.
This bit is an alias of CSR5, bit 10.
Reserved locations. Written as zeros and read as undefined.
Transmit Interrupt Enable. When this bit is set, the INTR bit will be set when the TINT bit in INT0 is
set.
This bit is an alias of CSR3, bit 9 with reversed polarity. (When TINTM in CSR3 is set, the transmit
interrupt is disabled.)
Previous devices in the PCnet family enable receive and transmit interrupts following reset. The
Am79C976 controller disables these interrupts following H_RESET (but not S_RESET). For
compatibility with legacy software, the Am79C976 controller will set RINTEN and TINTEN following
S_RESET. If, in addition, the user programs the EEPROM to load ones into RINTEN and TINTEN,
these interrupts will also be enabled after H_RESET. This matches the behavior of the previous
PCnet devices.
Value bit for byte 1. The value of this bit is written to any bits in the INTEN0 register that correspond
to bits in the INTEN0[6:0] bit map field that are set to 1.
Transmission Done Interrupt Enable. When this bit is set, the INTR bit will be set when the
TXDNINT bit in INT0 is set.
This bit is an alias of CSR5, bit 12.
Transmit Start Interrupt Enable. When this bit is set, the INTR bit will be set when the TXSTRTINT
bit in INT0 is set.
This bit is an alias of CSR4, bit 2.
Software Timer Interrupt Enable. When this bit is set, the INTR bit will be set when the STINT bit
in INT0 is set.
This bit is an alias of CSR7, bit 10.
Reserved locations. Written as zeros and read as undefined.
Receive Interrupt Enable. When this bit is set, the INTR bit will be set when the RINT bit in INT0 is
set.
This bit is an alias of CSR3, bit 10 with reversed polarity. (When RINTM in CSR3 is set, the receive
interrupt is disabled.)
Previous devices in the PCnet family enable receive and transmit interrupts following reset. The
Am79C976 controller disables these interrupts following H_RESET (but not S_RESET). For
compatibility with legacy software, the Am79C976 controller will set RINTEN and TINTEN following
S_RESET. If, in addition, the user programs the EEPROM to load ones into RINTEN and TINTEN,
these interrupts will also be enabled after H_RESET. This matches the behavior of the previous
PCnet devices.
P R E L I M I N A R Y
Am79C976
Description
8/01/00