AM79C976 Advanced Micro Devices, AM79C976 Datasheet - Page 113

• Manufacturer Part Number: AM79C976
• Description: PCnet-PRO 10/100 Mbps PCI Ethernet Controller
• Manufacturer: Advanced Micro Devices

0
Offset 06h
The PCI Status register is a 16-bit register that contains
status information for the PCI bus related events.
Bit
15
8/01/00
IOEN
Name
PERR
ting MEMEN. The Am79C976
controller will only respond to ac-
cesses to the Expansion ROM
when both ROMEN (PCI Expan-
sion ROM Base Address register,
bit 0) and MEMEN are set to 1.
Since MEMEN also enables the
memory mapped access to the
Am79C976 I/O resources, the
PCI Memory Mapped I/O Base
Address register must be pro-
grammed with an address so that
the device does not claim cycles
not intended for it.
MEMEN is cleared by H_RESET
and is not effected by S_RESET
or by setting the STOP bit.
Am79C976 controller will ignore
all I/O accesses when IOEN is
cleared. The host must set IOEN
before the first I/O access to the
device. The PCI I/O Base Ad-
dress register must be pro-
grammed with a valid I/O address
before setting IOEN.
IOEN is cleared by H_RESET
and is not effected by S_RESET
or by setting the STOP bit.
the Am79C976 controller detects
a parity error.
The Am79C976 controller sam-
ples the AD[31:0], C/BE[3:0], and
the PAR lines for a parity error at
the following times:
• In slave mode, during the ad-
dress phase of any PCI bus com-
mand.
• In slave mode, for all I/O, mem-
ory and configuration write com-
mands that select the Am79C976
controller when data is trans-
ferred (TRDY and IRDY are as-
serted).
I/O Space Access Enable. The
Parity Error. PERR is set when
Description
P R E L I M I N A R Y
Am79C976
14
13
12
SERR
RMABORT Received Master Abort. RM-
RTABORT
• In master mode, during the data
phase of all memory read com-
mands.
In master mode, during the data
phase of the memory write com-
mand, the Am79C976 controller
sets the PERR bit if the target re-
ports a data parity error by as-
serting the PERR signal.
PERR is not effected by the state
of the Parity Error Response en-
able bit (PCI Command register,
bit 6).
PERR is set by the Am79C976
controller and cleared by writing a
1. Writing a 0 has no effect.
PERR is cleared by H_RESET
and is not affected by S_RESET
or by setting the STOP bit.
SERR is set by the Am79C976
controller and cleared by writing a
1. Writing a 0 has no effect.
SERR is cleared by H_RESET
and is not affected by S_RESET
or by setting the STOP bit.
RMABORT
Am79C976
cleared by writing a 1. Writing a 0
has no effect. RMABORT is
cleared by H_RESET and is not
affected by S_RESET or by set-
ting the STOP bit.
RTABORT
Am79C976
when the Am79C976 controller
detects an address parity error
and both SERREN and PERREN
(PCI Command register, bits 8
and 6) are set.
ABORT
Am79C976 controller terminates
a master cycle with a master
abort sequence.
ABORT is set when a target ter-
minates an Am79C976 master
cycle with a target abort se-
quence.
Signaled SERR. SERR is set
Received
is
Target
is
is
set
controller
controller
set
set
Abort.
when
by
by
113
and
RT-
and
the
the
the