AM79C976 Advanced Micro Devices, AM79C976 Datasheet - Page 186

• Manufacturer Part Number: AM79C976
• Description: PCnet-PRO 10/100 Mbps PCI Ethernet Controller
• Manufacturer: Advanced Micro Devices

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DRTY
FCOLL
DXMTFCS Disable Transmit CRC (FCS).
to 1, the Am79C976 controller will
attempt only one transmission. In
this mode, the device will not pro-
tect the first 64 bytes of frame
data in the Transmit FIFO from
being overwritten, because auto-
matic retransmission will not be
necessary. When DRTY is set to
0, the Am79C976 controller will
attempt 16 transmissions before
signaling a retry error.
Read/Write accessible.
the collision logic to be tested.
The Am79C976 controller must
be in internal loopback for FCOLL
to be valid. If FCOLL = 1, a colli-
sion will be forced during loop-
back
which will result in a Retry Error.
If FCOLL = 0, the Force Collision
logic will be disabled. FCOLL is
defined after the initialization
block is read.
Read/Write accessible.
When DXMTFCS is set to 0, the
transmitter will generate and ap-
pend an FCS to the transmitted
frame. When DXMTFCS is set to
1, no FCS is generated or sent
with
DXMTFCS is overridden when
ADD_FCS and ENP bits are set
in the transmit descriptor.
which
APAD_XMT bit (CSR4, bit11),
adds padding to a frame, a valid
FCS field is appended to the
frame, regardless of the state of
DXMTFCS.
If
ADD_FCS is clear for a particular
frame, no FCS will be generated.
If ADD_FCS is set for a particular
frame, the state of DXMTFCS is
ignored and a FCS will be ap-
pended on that frame by the
transmit circuitry. See also the
ADD_FCS bit in the transmit de-
scriptor.
Disable Retry. When DRTY is set
Force Collision. This bit allows
When the auto padding logic,
DXMTFCS
the
transmission
is
transmitted
enabled
is
P R E L I M I N A R Y
set
attempts,
by
frame.
and
the
Am79C976
2
1
0
Bit
31-0
LOOP
0
0
1
LOOP
DTX
DRX
Name
RES
MIIILP
0
1
0
This bit was called DTCR in the
LANCE (Am7990) device.
Read/Write accessible.
Read/Write accessible.
Read/Write accessible.
Am79C976 controller to operate
in full-duplex mode for test pur-
poses. The setting of the full-
duplex control bits in BCR9 have
no effect when the device oper-
ates in loopback mode. When
LOOP = 1, loopback is enabled.
In combination with INTL and
MIIILP, various loopback modes
are defined as follows:.
Am79C976 controller not access-
ing the Transmit Descriptor Ring
and, therefore, no transmissions
are attempted. DTX = 0, will set
TXON bit (CSR0 bit 4) if STRT
(CSR0 bit 1) is asserted.
Disable Receiver results in the
Am79C976 controller not access-
ing the Receive Descriptor Ring
and, therefore, all receive frame
data are ignored. DRX = 0, will
set RXON bit (CSR0 bit 5) if
STRT (CSR0 bit 1) is asserted.
zeros and read as undefined.
Loopback Enable allows the
Disable
Description
Reserved locations. Written as
Refer to Loop Back Operation
section for more details.
Read/Write accessible. LOOP is
c l e a r e d b y H _ R E S E T o r
S_RESET and is unaffected by
STOP.
Normal Operation
Internal Loop
External Loop
Transmit
Function
results
8/01/00
in