M368L1713CTL-CA2 SAMSUNG [Samsung semiconductor], M368L1713CTL-CA2 Datasheet - Page 10

• Manufacturer Part Number: M368L1713CTL-CA2
• Description: 128MB DDR SDRAM MODULE (16Mx64 based on 16Mx8 DDR SDRAM) Unbuffered 184pin DIMM 64-bit Non-ECC/Parity
• Manufacturer: SAMSUNG [Samsung semiconductor]

M368L1713CTL
<Reference>
The following table specifies derating values for the specifications listed if the single-ended clock skew rate is less than 1.0 V/ns.
8. I/O Setup/Hold Plateau Derating
9. I/O Delta Rise/Fall Rate(1/slew-rate) Derating
10. This parameter is fir system simulation purpose. It is guranteed by design.
11. For each of the terms, if not already an integer, round to the next highest integer. tCK is actual to the system clock cycle time.
This derating table is used to increase tDS/tDH in the case where the input level is flat below VREF
This derating table is used to increase t
up to 2ns.
is calated as 1/SlewRate1-1/SlewRate2. For example, if slew rate 1 = 5V/ns and slew rate 2 =.4V/ns then the Delta Rise/Fall
Rate =-0/5ns/V. Input S/H slew rate based on larger of AC-AC delta rise/fall rate and DC-DC delta rise/fall rate.
(Single ended)
CK slew rate
Delta Rise/Fall Rate
0.75V/ns
1.0V/ns
0.5V/ns
I/O Input Level
(ns/V)
(mV)
0.25
0.5
280
0
+100
tIH/tIS
(ps)
+50
0
DS
/t
+100
(ps)
+50
(ps)
+50
D H
tDS
tDS
0
in the case where the DQ and DQS slew rates differ. The Delta Rise/Fall Rate
tDSS/tDSH
+100
(ps)
+50
184pin Unbuffered DDR SDRAM MODULE
0
+100
(ps)
+50
(ps)
+50
tDH
tDH
0
tAC/tDQSCK
+100
(ps)
+50
0
tLZ(min)
-100
(ps)
-50
0
310mV for a duration of
tHZ(max)
Rev. 0.3 May. 2002
+100
(ps)
+50
0