M368L1713CTL-CA2 SAMSUNG [Samsung semiconductor], M368L1713CTL-CA2 Datasheet - Page 8

• Manufacturer Part Number: M368L1713CTL-CA2
• Description: 128MB DDR SDRAM MODULE (16Mx64 based on 16Mx8 DDR SDRAM) Unbuffered 184pin DIMM 64-bit Non-ECC/Parity
• Manufacturer: SAMSUNG [Samsung semiconductor]

AC Timming Parameters & Specifications
M368L1713CTL
Row cycle time
Refresh row cycle time
Row active time
RAS to CAS delay
Row precharge time
Row active to Row active delay
Write recovery time
Last data in to Read command
Col. address to Col. address delay
Clock cycle time
Clock high level width
Clock low level width
DQS-out access time from CK/CK
Output data access time from CK/ CK
Data strobe edge to ouput data edge
Read Preamble
Read Postamble
CK to valid DQS-in
DQS-in setup time
DQS-in hold time
DQS falling edge to CK rising-setup time
DQS falling edge from CK rising-hold time
DQS-in high level width
DQS-in low level width
DQS-in cycle time
Address and Control Input setup time(fast)
Address and Control Input hold time(fast)
Address and Control Input setup time(slow)
Address and Control Input hold time(slow)
Data-out high impedence time from CK/ CK
Data-out low impedence time from CK/ CK
Input Slew Rate(for input only pins)
Input Slew Rate(for I/O pins)
Output Slew Rate(x4,x8)
Output Slew Rate Matching Ratio(rise to fall)
Parameter
CL=2.0
CL=2.5
Symbol
tWPRES
tDQSCK
tWPRE
tDQSQ
tDQSS
tDQSH
tSL(IO)
tRPRE
tRPST
tDQSL
tSL(O)
tSLMR
tWTR
tRFC
tRAS
tRCD
tRRD
tCCD
tDSS
tDSH
tDSC
tSL(I)
tWR
tRC
tCH
tRP
tCK
tCL
tAC
tHZ
tLZ
tIS
tIH
tIS
tIH
184pin Unbuffered DDR SDRAM MODULE
Min
0.45
0.45
0.75
0.25
0.35
0.35
0.75
0.75
0.67
-0.6
-0.7
-0.7
-0.7
7.5
0.9
0.4
0.2
0.2
0.9
0.8
0.8
0.5
0.5
1.0
60
72
42
18
18
12
15
1
1
6
0
-
(DDR333)
(These AC charicteristics were tested on the Component)
-TCB3
Max
0.55
0.55
+0.6
+0.7
0.45
1.25
+0.7
+0.7
70K
1.1
0.6
1.1
4.5
1.5
12
12
-0.75
-0.75
-0.75
-0.75
Min
0.45
0.45
0.75
0.25
0.35
0.35
0.67
7.5
7.5
0.9
0.4
0.2
0.2
0.9
0.9
0.9
1.0
1.0
0.5
0.5
1.0
65
75
45
20
20
15
15
1
1
0
-
(DDR266A)
-TCA2
+0.75
+0.75
120K
Max
+0.75
+0.75
0.55
0.55
1.25
0.5
1.1
0.6
1.1
4.5
1.5
12
12
-0.75
-0.75
-0.75
-0.75
Min
0.45
0.45
0.75
0.25
0.35
0.35
0.67
7.5
0.9
0.4
0.2
0.2
0.9
0.9
0.9
1.0
1.0
0.5
0.5
1.0
65
75
45
20
20
15
15
10
1
1
0
(DDR266B)
-
-TCB0
Rev. 0.3 May. 2002
120K
+0.75
+0.75
Max
+0.75
+0.75
0.55
0.55
1.25
0.5
1.1
0.6
1.1
4.5
1.5
12
12
Unit
V/ns
V/ns
V/ns
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note
10
5
5
5
2
6
6
6
6
6
7