M368L1713CTL-CA2 SAMSUNG [Samsung semiconductor], M368L1713CTL-CA2 Datasheet - Page 5

• Manufacturer Part Number: M368L1713CTL-CA2
• Description: 128MB DDR SDRAM MODULE (16Mx64 based on 16Mx8 DDR SDRAM) Unbuffered 184pin DIMM 64-bit Non-ECC/Parity
• Manufacturer: SAMSUNG [Samsung semiconductor]

ABSOLUTE MAXIMUM RATINGS
Note :
Notes 1. Includes 25mV margin for DC offset on V
Recommended operating conditions(Voltage referenced to V
POWER & DC OPERATING CONDITIONS (SSTL_2 In/Out)
M368L1713CTL
Voltage on any pin relative to Vss
Voltage on V
Voltage on V
Storage temperature
Power dissipation
Short circuit current
Supply voltage(for device with a nominal V
I/O Supply voltage
I/O Reference voltage
I/O Termination voltage(system)
Input logic high voltage
Input logic low voltage
Input Voltage Level, CK and CK inputs
Input Differential Voltage, CK and CK inputs
Input crossing point voltage, CK and CK inputs
Input leakage current
Output leakage current
Output High Current(Normal strengh driver)
Output High Current(Normal strengh driver)
Output High Current(Half strengh driver)
Output High Current(Half strengh driver)
;V
;V
;V
;V
OUT
OUT
OUT
OUT
6. These charactericteristics obey the SSTL-2 class II standards.
5. The value of V
2.V
3. V
4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on V
TO V
V
= V
= V
= V
= V
TT
simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ.
REF
ID
TT
TT
is not applied directly to the device. V
is the magnitude of the difference between the input level on CK and the input level on CK.
TT
TT
, and must track variations in the DC level of V
D D
DDQ
REF
Parameter
+ 0.84V
+ 0.45V
- 0.84V
- 0.45V
supply relative to Vss
, both of which may result in V
supply relative to Vss
Parameter
IX
is expected to equal 0.5*V
DD
REF
of 2.5V)
TT
noise. V
REF
DDQ
is a system supply for signal termination resistors, is expected to be set equal to
V
Symbol
184pin Unbuffered DDR SDRAM MODULE
, and a combined total of 50mV margin for all AC noise and DC offset on V
I N
V
of the transmitting device and must track variations in the dc level of the same.
T
V
, V
I
P
DDQ
STG
OS
DD
D
REF
R E F
OUT
SS
Symbol
V
V
V
V
V
V
=0V, T
V
IH
IN
ID
IL
IX
V
V
should be de-coupled with an inductance of
I
I
I
I
I
DDQ
R E F
(DC)
O Z
O H
O H
(DC)
(DC)
(DC)
(DC)
OL
OL
DD
I
TT
I
A
=0 to 70 C)
VDDQ/2-50mV
V
V
R E F
REF
-16.8
1.15
16.8
Min
-0.3
-0.3
2.3
2.3
0.3
-2
-5
-9
9
+0.15
-0.04
-55 ~ +150
-0.5 ~ 3.6
-1.0 ~ 3.6
-1.0 ~ 3.6
Value
12
50
VDDQ/2+50mV
V
V
V
V
V
REF
R E F
REF
DDQ
DDQ
DDQ
Max
1.35
2.7
2.7
2
5
+0.04
-0.15
and internal DRAM noise coupled
+0.3
+0.3
+0.6
Rev. 0.3 May. 2002
3nH.
Unit
mA
mA
mA
mA
uA
uA
V
V
V
V
V
V
V
V
Unit
mA
W
V
V
V
C
Note
1
2
4
4
3
5
REF
,