M368L1713CTL-CA2 SAMSUNG [Samsung semiconductor], M368L1713CTL-CA2 Datasheet - Page 11

• Manufacturer Part Number: M368L1713CTL-CA2
• Description: 128MB DDR SDRAM MODULE (16Mx64 based on 16Mx8 DDR SDRAM) Unbuffered 184pin DIMM 64-bit Non-ECC/Parity
• Manufacturer: SAMSUNG [Samsung semiconductor]

Command Truth Table
M368L1713CTL
Register
Register
Refresh
Bank Active & Row Addr.
Read &
Column Address
Write &
Column Address
Burst Stop
Precharge
Active Power Down
Precharge Power Down Mode
DM
No operation (NOP) : Not defined
Note : 1. OP Code : Operand Code. A
2. EMRS/ MRS can be issued only at all banks precharge state.
4. BA
5. If A
8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).
3. Auto refresh functions are same as the CBR refresh of DRAM.
6. During burst write with auto precharge, new read/write command can not be issued.
7. Burst stop command is valid at every burst length.
9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.
New row active of the associated bank can be issued at t
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
If both BA
If BA
If BA
If both BA
Another bank read/write command can be issued after the end of burst.
A new command can be issued 2 clock cycles after EMRS or MRS.
0
10
~ BA
0
0
/AP is "High" at row precharge, BA
is "High" and BA
is "Low" and BA
COMMAND
1
0
0
Extended MRS
Mode Register Set
Auto Refresh
Self
Refresh
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Disable
Auto Precharge Enable
Bank Selection
All Banks
: Bank select addresses.
and BA
and BA
1
1
are "Low" at read, write, row active and precharge, bank A is selected.
are "High" at read, write, row active and precharge, bank D is selected.
1
1
is "High" at read, write, row active and precharge, bank C is selected.
is "Low" at read, write, row active and precharge, bank B is selected.
Entry
Entry
Entry
Exit
Exit
Exit
0
~ A
11
& BA
CKEn-1
0
H
H
H
H
H
H
H
H
H
H
H
H
and BA
L
L
L
0
184pin Unbuffered DDR SDRAM MODULE
~ BA
1
CKEn
1
are ignored and all banks are selected.
(V=Valid, X=Don t Care, H=Logic High, L=Logic Low)
X
X
H
H
X
X
X
X
X
H
H
X
: Program keys. (@EMRS/MRS)
L
L
L
RP
CS
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
X
L
L
L
after the end of burst.
RAS
X
H
X
H
H
H
X
V
X
X
H
X
V
X
H
L
L
L
L
L
CAS
H
X
H
H
H
X
V
X
X
H
X
V
X
H
L
L
L
L
L
WE
H
H
X
H
H
X
V
X
X
H
X
V
X
H
L
L
L
L
L
BA
V
V
V
V
X
0,1
Rev. 0.3 May. 2002
A
OP CODE
OP CODE
10
H
H
H
Row Address
L
L
L
/AP
X
X
X
X
X
X
X
A
Address
Address
Column
Column
(A
(A
9
A
0
0
~ A
X
~ A
~ A
11
9
9
0
)
)
Note
1, 2
1, 2
4, 6
3
3
3
3
4
4
4
7
5
8
9
9