M368L1713CTL-CA2 SAMSUNG [Samsung semiconductor], M368L1713CTL-CA2 Datasheet - Page 9

• Manufacturer Part Number: M368L1713CTL-CA2
• Description: 128MB DDR SDRAM MODULE (16Mx64 based on 16Mx8 DDR SDRAM) Unbuffered 184pin DIMM 64-bit Non-ECC/Parity
• Manufacturer: SAMSUNG [Samsung semiconductor]

1. Maximum burst refresh cycle : 8
2. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from
3. The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter,
4. A write command can be applied with t
5. For registered DIMMs, t
6. Input Setup/Hold Slew Rate Derating
7. I/O Setup/Hold Slew Rate Derating
M368L1713CTL
Mode register set cycle time
DQ & DM setup time to DQS
DQ & DM hold time to DQS
Control & Address input pulse width
DQ & DM input pulse width
Power down exit time
Exit self refresh to non-Read command
Exit self refresh to read command
Refresh interval time
Output DQS valid window
Clock half period
Data hold skew factor
DQS write postamble time
Active to Read with Auto precharge
command
Autoprecharge write recovery +
Precharge time
This derating table is used to increase t
based on the lesser of AC-AC slew rate and DC-DC slew rate.
based on the lesser of AC-AC slew rate and DC-DC slew rate.
This derating table is used to increase t
but system performance (bus turnaround) will degrade accordingly.
jitter due to crosstalk (t
High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress,
DQS could be High at this time, depending on tDQSS.
Input Setup/Hold Slew Rate
I/O Setup/Hold Slew Rate
Parameter
(V/ns)
(V/ns)
0.5
0.4
0.3
0.5
0.4
0.3
JIT
CL
(crosstalk)
and t
CH
Symbol
are
) on the DIMM.
tWPST
tPDEX
tXSNR
tXSRD
tDIPW
tMRD
tREFI
tQHS
tRAP
tIPW
tDAL
tDH
tQH
tDS
tHP
RCD
DS
IS
45% of the period including both the half period jitter (t
/t
/t
+100
IH
+150
DH
(ps)
+50
(ps)
+75
satisfied after this command.
tDS
tIS
0
0
in the case where the input slew rate is below 0.5V/ns. Input setup/hold slew rate
or tCHmin
(tWR/tCK)
(tRP/tCK)
in the case where the I/O slew rate is below 0.5V/ns. I/O setup/hold slew rate
tCLmin
-tQHS
Min
0.45
0.45
1.75
15.6
200
tHP
2.2
0.4
12
75
20
6
+
(DDR266A)
-TCB3
184pin Unbuffered DDR SDRAM MODULE
Max
0.55
+100
+150
0.6
(ps)
+50
(ps)
+75
tDH
-
-
tIH
0
0
or tCHmin
(tWR/tCK)
(tRP/tCK)
tCLmin
-tQHS
Min
1.75
15.6
200
tHP
0.5
0.5
2.2
7.5
0.4
15
75
20
+
(DDR266A)
-TCA2
Max
0.75
0.6
-
-
or tCHmin
(tWR/tCK)
(tRP/tCK)
JIT(HP)
tCLmin
-tQHS
Min
1.75
15.6
200
tHP
0.5
0.5
2.2
7.5
0.4
15
75
20
+
(DDR266B)
) of the PLL and the half period
-TCB0
Rev. 0.3 May. 2002
Max
0.75
0.6
-
-
Unit
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
us
ns
ns
ns
Note
7,8,9
7,8,9
11
4
1
5
3