M368L1713CTL-CA2 SAMSUNG [Samsung semiconductor], M368L1713CTL-CA2 Datasheet - Page 3

• Manufacturer Part Number: M368L1713CTL-CA2
• Description: 128MB DDR SDRAM MODULE (16Mx64 based on 16Mx8 DDR SDRAM) Unbuffered 184pin DIMM 64-bit Non-ECC/Parity
• Manufacturer: SAMSUNG [Samsung semiconductor]

M368L1713CTL DDR SDRAM 184pin DIMM
16Mx64 DDR SDRAM 184pin DIMM based on 16Mx8
M368L1713CTL
PIN CONFIGURATIONS (Front side/back side)
GENERAL DESCRIPTION
Rate SDRAM high density memory modules.
The Samsung M368L1713CTL consists of eight CMOS 16M x
8 bit with 4banks Double Data Rate SDRAMs in 66pin TSOP-
II(400mil) packages mounted on a 184pin glass-epoxy sub-
strate. Four 0.1uF decoupling capacitors are mounted on the
printed circuit board in parallel for each DDR SDRAM. The
M368L1713CTL is Dual In-line Memory Modules and intended
for mounting into 184pin edge connector sockets.
of system clock. Data I/O transactions are possible on both
edges of DQS. Range of operating frequencies, programmable
latencies and burst lengths allow the same device to be useful
for a variety of high bandwidth, high performance memory sys-
tem applications.
Pin Front
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
The Samsung M368L1713CTL is 16M bit x 64 Double Data
1
2
3
4
5
6
7
8
9
Synchronous design allows precise cycle control with the use
VDDQ
VDDQ
VDDQ
DQS0
DQS1
DQS2
VREF
DQ10
DQ11
CKE0
DQ16
DQ17
DQ18
DQ19
VDD
/CK1
DQ0
VSS
DQ1
DQ2
DQ3
VSS
DQ8
DQ9
CK1
VSS
VSS
NC
NC
A9
A7
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Pin Front Pin
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
KEY
*DQS8
VDDQ
DQ24
DQ25
DQS3
DQ26
DQ27
DQ32
DQ33
DQS4
DQ34
DQ35
DQ40
*CB0
*CB1
*CB2
*CB3
VSS
VDD
VSS
VDD
VSS
VSS
BA1
BA0
A5
A4
A2
A1
A0
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
VDDID
VDDQ
DQS5
VDDQ
DQS6
DQS7
Front
DQ41
DQ42
DQ43
*/CS2
DQ48
DQ49
DQ50
DQ51
DQ56
DQ57
DQ58
DQ59
/CAS
VDD
/CK2
VDD
VSS
VSS
CK2
VSS
VSS
SDA
SCL
/WE
NC
Pin
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
93
94
95
96
97
98
99
*CKE1
VDDQ
VDDQ
VDDQ
DQ12
DQ13
DQ14
DQ15
DQ20
DQ21
DQ22
DQ23
Back
*BA2
VSS
DQ4
DQ5
DM0
DQ6
DQ7
VSS
DM1
VDD
*A12
VSS
DM2
VDD
A11
NC
NC
NC
A8
Pin
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
184pin Unbuffered DDR SDRAM MODULE
KEY
VDDQ
VDDQ
VDDQ
DQ28
DQ29
DQ30
DQ31
*DM8
DQ36
DQ37
DQ38
DQ39
DQ44
Back
*CB4
*CB5
*CB6
*CB7
DM3
/CK0
VDD
DM4
VSS
VSS
CK0
VSS
VSS
VSS
A10
A6
A3
Pin
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
• Performance range
• Power supply : Vdd: 2.5V ± 0.2V, Vddq: 2.5V ± 0.2V
•
• Bidirectional data strobe(DQS)
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• Programmable Read latency 2, 2.5 (clock)
• Programmable Burst length (2, 4, 8)
• Programmable Burst type (sequential & interleave)
• Edge aligned data output, center aligned data input
• Auto & Self refresh, 15.6us refresh interval(4K/64ms refresh)
• Serial presence detect with EEPROM
• PCB : Height 1250 mil , double sided component
FEATURE
M368L1713CTL-C(L)B3 166MHz(6ns@CL=2.5)
M368L1713CTL-C(L)A2 133MHz(7.5ns@CL=2)
M368L1713CTL-C(L)B0 133MHz(7.5ns@CL=2.5)
Double-data-rate architecture; two data transfers per clock cycle
VDDSPD
VDDQ
VDDQ
VDDQ
VDDQ
DQ45
*/CS1
DQ46
DQ47
*/CS3
DQ52
DQ53
DQ54
DQ55
DQ60
DQ61
DQ62
DQ63
Back
/RAS
/CS0
DM5
VSS
*A13
VDD
DM6
VSS
DM7
SA0
SA1
SA2
NC
Part No.
PIN DESCRIPTION
*
A0 ~ A11
BA0 ~ BA1
DQ0 ~ DQ63
DQS0 ~ DQS7
CK0,CK0 ~ CK2,CK2 Clock input
CKE0
/CS0
RAS
CAS
WE
DM0 ~ DM7
VDD
VDDQ
VSS
VREF
VDDSPD
SDA
SCL
SA0 ~ 2
VDDID
NC
These pins are not used in this module.
Pin Name
Max Freq.
Rev. 0.3 May. 2002
Address input (Multiplexed)
Bank Select Address
Data input/output
Data Strobe input/output
Clock enable input
Chip select input
Row address strobe
Column address strobe
Write enable
Data - in mask
Power supply (2.5V)
Power Supply for DQ S(2.5V)
Ground
Power supply for reference
Serial EEPROM Power
Supply (2.3V to 3.6V)
Serial data I/O
Serial clock
Address in EEPROM
VDD identification flag
No connection
Function
Interface
SSTL_2