HYS64T128020EDL-2.5-B QIMONDA [Qimonda AG], HYS64T128020EDL-2.5-B Datasheet - Page 24

• Manufacturer Part Number: HYS64T128020EDL-2.5-B
• Description: 200-Pin Small-Outlined DDR2 SDRAM Modules
• Manufacturer: QIMONDA [Qimonda AG]

3.4
List of tables defining
Rev. 1.12, 2007-10
10312006-I253-V1V0
Parameter
Operating Current 0
One bank Active - Precharge;
valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING.
Operating Current 1
One bank Active - Read - Precharge;
t
control inputs are SWITCHING, Databus inputs are SWITCHING.
Precharge Standby Current
All banks idle; CS is HIGH; CKE is HIGH;
Databus inputs are SWITCHING.
Precharge Power-Down Current
Other control and address inputs are STABLE, Data bus inputs are FLOATING.
Precharge Quiet Standby Current
All banks idle; CS is HIGH; CKE is HIGH;
Data bus inputs are FLOATING.
Active Standby Current
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CL
t
SWITCHING; Data Bus inputs are SWITCHING;
Active Power-Down Current
All banks open;
are FLOATING. MRS A12 bit is set to LOW (Fast Power-down Exit);
Active Power-Down Current
All banks open; t
are FLOATING. MRS A12 bit is set to HIGH (Slow Power-down Exit);
Operating Current - Burst Read
All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CL
t
bus inputs are SWITCHING;
Operating Current - Burst Write
All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CL
t
SWITCHING; Data Bus inputs are SWITCHING;
Burst Refresh Current
t
commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
Distributed Refresh Current
t
commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
RCD
RAS
RP
RAS
CK
CK
=
=
=
=
=
=
t
t
t
RPMIN
CK.MIN
CK.MIN.
t
t
t
RAS.MAX
RAS.MAX.
RCD.MIN
; CKE is HIGH, CS is HIGH between valid commands; Address inputs are SWITCHING; Data
., Refresh command every
, Refresh command every
, AL = 0, CL = CL
,
,
t
t
t
RP
CK
CK
RP
=
=
=
=
I
t
t
t
I
t
RP.MIN
CK.MIN
CK.MIN
RP.MAX
DD
DD
Specifications and Conditions.
; CKE is HIGH, CS is HIGH between valid commands. Address inputs are
, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs
, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs
Specifications and Conditions
; CKE is HIGH, CS is HIGH between valid commands. Address inputs are
I
t
OUT
CK
MIN
=
= 0mA.
; CKE is HIGH, CS is HIGH between valid commands. Address and
t
CK.MIN
I
t
OUT
t
RFC
RFC
,
t
CK
t
t
= 0 mA, BL = 4,
RC
CK
=
=
=
t
t
=
=
REFI
t
RFC.MIN
CK.MIN
t
t
RC.MIN
CK.MIN
I
OUT
interval, CKE is LOW and CS is HIGH between valid
; Other control and address inputs are SWITCHING,
interval, CKE is HIGH, CS is HIGH between valid
,
; Other control and address inputs are STABLE,
= 0 mA.
t
RAS
=
t
CK
t
24
RAS.MIN
=
t
MIN
CK.MIN
MIN
, CKE is HIGH, CS is HIGH between
;
;
t
t
CK
CK
,
t
RC
=
=
t
t
CKMIN
=
CK.MIN
t
MIN
RC.MIN
;
Small Outlined DDR2 SDRAM Modules
;
;
t
t
RAS
CK
,
HYS64T128020EDL–[2.5/3S/3.7]–B
t
=
RAS
=
t
CK.MIN
t
RASMAX
=
I
DD
t
RAS.MIN
;
Measurement Conditions
;
,
Internet Data Sheet
Symbol Note
I
I
I
I
I
I
I
I
I
I
I
I
DD0
DD1
DD2N
DD2P
DD2Q
DD3N
DD3P(0)
DD3P(1)
DD4R
DD4W
DD5B
DD5D
TABLE 18
3)4)5)
6)
6)
1)2)