HYS64T128020HU-5-B QIMONDA [Qimonda AG], HYS64T128020HU-5-B Datasheet - Page 21

• Manufacturer Part Number: HYS64T128020HU-5-B
• Description: 240-Pin unbuffered DDR2 SDRAM Modules
• Manufacturer: QIMONDA [Qimonda AG]

1) For details and notes see the relevant Qimonda component data sheet
2)
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
Parameter
DQ and DM input pulse width for each input
DQS output access time from CK / CK
DQS input high pulse width
DQS input low pulse width
DQS-DQ skew for DQS & associated DQ signals
DQS latching rising transition to associated clock
edges
DQ and DM input setup time
DQS falling edge hold time from CK
DQS falling edge to CK setup time
CK half pulse width
Data-out high-impedance time from CK / CK
Address and control input hold time
Control & address input pulse width for each input
Address and control input setup time
DQ low impedance time from CK/CK
DQS/DQS low-impedance time from CK / CK
MRS command to ODT update delay
Mode register set command cycle time
OCD drive mode output delay
DQ/DQS output hold time from DQS
DQ hold skew factor
Read preamble
Read postamble
Internal Read to Precharge command delay
Write preamble
Write postamble
Write recovery time
Internal write to read command delay
Exit power down to read command
Exit active power-down mode to read command
(slow exit, lower power)
Exit precharge power-down to any valid
command (other than NOP or Deselect)
Exit self-refresh to a non-read command
Exit self-refresh to read command
Write command to DQS associated clock edges
V
DDQ
= 1.8 V ± 0.1V;
V
DD
= 1.8 V ± 0.1 V. See notes
5)6)7)8)
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
WL
DIPW
DQSCK
DQSH
DQSL
DQSQ
DQSS
DS.BASE
DSH
DSS
HP
HZ
IH.BASE
IPW
IS.BASE
LZ.DQ
LZ.DQS
MOD
MRD
OIT
QH
QHS
RPRE
RPST
RTP
WPRE
WPST
WR
WTR
XARD
XARDS
XP
XSNR
XSRD
21
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
DDR2–800
0.35
–350
0.35
0.35
—
– 0.25
50
0.2
0.2
Min(
t
—
250
0.6
175
2 x
t
0
2
0
t
—
0.9
0.4
7.5
0.35
0.4
15
7.5
2
8 – AL
2
t
200
RL – 1
Min.
CL.ABS
AC.MIN
HP
RFC
–
t
t
AC.MIN
+10
CH.ABS
t
)
QHS
,
Max.
—
+350
—
—
200
+ 0.25
––
—
—
__
t
—
—
—
t
t
12
—
12
—
300
1.1
0.6
—
—
0.6
—
—
—
—
—
—
—
AC.MAX
AC.MAX
AC.MAX
Unbuffered DDR2 SDRAM Module
Unit
t
ps
t
t
ps
t
ps
t
t
ps
ps
ps
t
ps
ps
ps
ns
nCK
ns
ps
ps
t
t
ns
t
t
ns
ns
nCK
nCK
nCK
ns
nCK
nCK
CK.AVG
CK.AVG
CK.AVG
CK.AVG
CK.AVG
CK.AVG
CK.AVG
CK.AVG
CK.AVG
CK.AVG
CK.AVG
Internet Data Sheet
Note
1)2)3)4)5)6)7)8)
9)
16)
17)
18)19)20)
17)
17)
21)
9)22)
23)25)
24)25)
9)22)
9)22)
31)
31)
26)
27)
28)29)
28)30)
31)
31)
31)32)
31)