HYS64T128020HU-5-B QIMONDA [Qimonda AG], HYS64T128020HU-5-B Datasheet - Page 4

• Manufacturer Part Number: HYS64T128020HU-5-B
• Description: 240-Pin unbuffered DDR2 SDRAM Modules
• Manufacturer: QIMONDA [Qimonda AG]

1.2
The Qimonda HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
module family are unbuffered DIMM modules “UDIMMs” with
30 mm height based on DDR2 technology. DIMMs are
available as non-ECC modules in 32M × 64 (256 MB),
64M × 64 (512 MB), 128M × 64(1 GB) and as ECC modules
in 64M × 72 (512 MB), 128M × 72(1 GB) organization and
density, intended for mounting into 240-pin connector
sockets.
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
Product Type
PC2–6400
HYS64T32000HU–25F–B
HYS64T64000HU–25F–B
HYS72T64000HU–25F–B
HYS64T128020HU–25F–B
HYS72T128020HU–25F–B
PC2–6400
HYS64T32000HU–2.5–B
HYS64T64000HU–2.5–B
HYS72T64000HU–2.5–B
HYS64T128020HU–2.5–B
HYS72T128020HU–2.5–B
PC2–5300
HYS64T32000HU–3–B
HYS64T64000HU–3–B
HYS72T64000HU–3–B
HYS64T128020HU–3–B
HYS72T128020HU–3–B
PC2–5300
HYS64T32000HU–3S–B
HYS64T32900HU–3S–B
HYS64T64000HU–3S–B
HYS64T64900HU–3S–B
HYS72T64000HU–3S–B
HYS64T128020HU–3S–B
HYS64T128920HU–3S–B
HYS72T128020HU–3S–B
1)
Description
Compliance Code
256 MB 1R×16 PC2–6400U–555–12–C1
512 MB 1R×8 PC2–6400U–555–12–D0
512 MB 1R×8 PC2–6400E–555–12–F0
1 GB 2R×8 PC2–6400U–555–12–E0
1 GB 2R×8 PC2–6400E–555–12–G0
256 MB 1R×16 PC2–6400U–666–12–C1
512 MB 1R×8 PC2–6400U–666–12–D0
512 MB 1R×8 PC2–6400E–666–12–F0
1 GB 2R×8 PC2–6400U–666–12–E0
1 GB 2R×8 PC2–6400E–666–12–G0
256 MB 1R×16 PC2–5300U–444–12–C1
512 MB 1R×8 PC2–5300U–444–12–D0
512 MB 1R×8 PC2–5300E–444–12–F0
1 GB 2R×8 PC2–5300U–444–12–E0
1 GB 2R×8 PC2–5300E–444–12–G0
256 MB 1R×16 PC2–5300U–555–12–C1
256 MB 1R×16 PC2–5300U–555–12–C1
512 MB 1R×8 PC2–5300U–555–12–D0
512 MB 1R×8 PC2–5300U–555–12–D0
512 MB 1R×8 PC2–5300E–555–12–F0
1 GB 2R×8 PC2–5300U–555–12–E0
1 GB 2R×8 PC2–5300U–555–12–E0
1 GB 2R×8 PC2–5300E–555–12–G0
2)
4
Ordering Information for RoHS Compliant Products
The memory array is designed with 512-Mbit Double-Data-
Rate-Two
capacitors are mounted on the PCB board. The DIMMs
feature serial presence detect based on a serial E
device using the 2-pin I
programmed with configuration data and are write protected;
the second 128 bytes are available to the customer.
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
(DDR2)
Description
1 Rank, Non-ECC
1 Rank, Non-ECC
1 Rank, ECC
2 Ranks, Non-ECC
2 Ranks, ECC
1 Rank, Non-ECC
1 Rank, Non-ECC
1 Rank, ECC
2 Ranks, Non-ECC
2 Ranks, ECC
1 Rank, Non-ECC
1 Rank, Non-ECC
1 Rank, ECC
2 Ranks, Non-ECC
2 Ranks, ECC
1 Rank, Non-ECC
1 Rank, Non-ECC
1 Rank, Non-ECC
1 Rank, Non-ECC
1 Rank, ECC
2 Ranks, Non-ECC
2 Ranks, Non-ECC
2 Ranks, ECC
Unbuffered DDR2 SDRAM Module
Synchronous
2
C protocol. The first 128 bytes are
DRAMs.
Internet Data Sheet
SDRAM
Technology
512 Mbit (×16)
512 Mbit (×8)
512 Mbit (×8)
512 Mbit (×8)
512 Mbit (×8)
512 Mbit (×16)
512 Mbit (×8)
512 Mbit (×8)
512 Mbit (×8)
512 Mbit (×8)
512 Mbit (×16)
512 Mbit (×8)
512 Mbit (×8)
512 Mbit (×8)
512 Mbit (×8)
512 Mbit (×16)
512 Mbit (×16)
512 Mbit (×8)
512 Mbit (×8)
512 Mbit (×8)
512 Mbit (×8)
512 Mbit (×8)
512 Mbit (×8)
TABLE 2
Decoupling
2
PROM