HYS64T128020HU-5-B QIMONDA [Qimonda AG], HYS64T128020HU-5-B Datasheet - Page 30
HYS64T128020HU-5-B
Manufacturer Part Number
HYS64T128020HU-5-B
Description
240-Pin unbuffered DDR2 SDRAM Modules
Manufacturer
QIMONDA [Qimonda AG]
Datasheet
1.HYS64T128020HU-5-B.pdf
(87 pages)
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13) The
14) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range between 85 °C
15) 0 °C≤
16) 85 °C <
17) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device.
18) The
19) The maximum limit for the
20) Minimum
21) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In “standard active power-
22) WR must be programmed to fulfill the minimum requirement for the
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
(
parameters are verified by design and characterization, but not subject to production test.
and 95 °C.
Compliant Products” on Page
performance (bus turnaround) degrades accordingly.
down mode” (MR, A12 = “0”) a fast power-down exit timing
power-down exit timing
up to the next integer value.
refers to the application clock period. WR refers to the WR parameter stored in the MRS.
t
HZ,
t
t
t
HZ
RPST
RRD
T
,
CASE
T
t
RPST
), or begins driving (
timing parameter depends on the page size of the DRAM organization. See
CASE
t
WTR
≤ 85 °C
and
≤ 95 °C
is two clocks when operating the DDR2-SDRAM at frequencies ≤ 200 ΜΗz.
t
LZ
,
t
RPRE
t
XARDS
t
parameters are referenced to a specific voltage level, which specify when the device output is no longer driving
WPST
t
t
DAL
LZ,
has to be satisfied.
t
parameter is not a device limit. The device operates with a greater value for this parameter, but system
4.
= WR + (
RPRE
).
t
HZ
t
RP
and
/
t
CK
t
LZ
). For each of the terms, if not already an integer, round to the next highest integer.
transitions occur in the same access time windows as valid data transitions.These
t
XARD
30
can be used. In “low active power-down mode” (MR, A12 =”1”) a slow
t
WR
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
timing parameter, where
Table 2 “Ordering Information for RoHS
Unbuffered DDR2 SDRAM Module
WR
MIN
[cycles] =
Internet Data Sheet
t
WR
(ns)/
t
CK
(ns) rounded
t
CK
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