HD66717A03TA0 HITACHI [Hitachi Semiconductor], HD66717A03TA0 Datasheet
HD66717A03TA0
Related parts for HD66717A03TA0
HD66717A03TA0 Summary of contents
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Dot-Matrix Liquid Crystal Display Description The HD66717 dot-matrix liquid crystal display controller and driver LSI displays alphanumerics, katakana, hiragana, and symbols. It can be configured to drive a dot-matrix liquid crystal display under 2 the control ...
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... Note: Current consumption excludes that for LCD power supply source; V List 2 Ordering Information Type Name External Dimensin HD66717A03TA0 TCP HCD66717A03 Bare chip HCD66717A03BP Au-bumped chip HCD66717A13BP Au-bumped chip Current Multi-plexed-Drive Consumption Segments 8 µ µ ...
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HD66717 LCD-II Family Comparison LCD-II Item (HD44780U) Power supply voltage 2.7V to 5.5V Liquid crystal drive voltage 3.0 to 11.0V Maximum display - 8 characters characters per chip 2 lines Segment display None Display duty ratio 1/8, 1/11, and 1/16 ...
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LCD-II Family Comparison (cont) Item HD66720 Power supply voltage 2.7V to 5.5V Liquid crystal drive voltage 3.0 to 11.0V Maximum display 10 characters characters per chip 1 line/ 8 characters 2 lines Segment display 42 (extended to 80) Display duty ...
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HD66717 HD66717 Block Diagram RESET* TEST Instruction register (IR) 8 IM1/0 System RS/CS* interface 2 • bus 7 E/SCL • Clock- synchro- RW/SDA nized serial • 4 bits • 8 bits 8 Data DB7–DB6 register (DR) Input/ output ...
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HD66717 Pin Arrangement Dummy Dummy Dummy Dummy V1OUT V2OUT V3OUT V4OUT V5OUT VREFP VREF VREFM V5OUT3 V5OUT3 V5OUT2 V5OUT2 Vci Vci GND GND Dummy V CC ...
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HD66717 458 ...
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TCP Dimensions V5OUT3 V5OUT2 I/O, Power supply 0.50P (44–1) = 21.50mm RESET* RW/SDA DB0/ID0 DB1/ID1 DB2/ID2 DB3/ID3 DB4/ID4 DB5/ID5 Dummy Dummy COMS1 NC COM32 V CC V1OUT V2OUT V3OUT V4OUT V5OUT COM17 VREFP 0.50mm SEG60 VREF VREFM pitch 0.22 mm ...
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HD66717 Pin Functions Table 1 Pin Functional Description Number Device Signal of Pins I/O Interfaced with Function IM1, IM0 GND CC RS/CS MPU RW/SDA 1 I/O, I MPU E/SCL 1 I MPU DB7, 4 ...
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Table 1 Pin Functional Description (cont) Number Device Signal of Pins I/O Interfaced with Function COM1 LCD COM32 SEG1 LCD SEG60 ACOM 1 O LCD ASEG1 LCD ASEG10 V2/ ...
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HD66717 Table 1 Pin Functional Description (cont) Number Device Signal of Pins I/O Interfaced with Function Vci 2 I Power supply V5OUT2 pin/ Booster EE capacitance V5OUT3 pin EE C1/C2 2 — Booster capacitance ...
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Block Function Description System Interface The HD66717 has four types of system interfaces: I bus. The interface mode is selected by the IM1 and IM0 pins. The HD66717 has two 8-bit registers: an instruction register (IR) and a data register ...
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HD66717 Table 2 Register Selection RS R/W Operation write as an internal operation (display clear, etc Read busy flag (DB7) read and address counter (DB0 to DB6) (4/8-bit bus interface write as ...
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Table 4 Display-Line Modes, Display-Start Line, and DDRAM Addresses Display- Duty Line Mode Ratio Common Pins 1-line 1/10 COM1–COM8 (NL = 00) 2-line 1/18 COM1–COM8 (NL = 01) COM9–COM16 3-line 1/26 COM1–COM8 (NL = 10) COM9–COM16 COM17–COM24 4-line 1/34 COM1–COM8 ...
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HD66717 Timing Generation Circuit The timing generation circuit generates timing signals for the operation of internal circuits such as DDRAM, CGROM, CGRAM, and SEGRAM. RAM read timing for display and internal operation timing by MPU access are generated separately to ...
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Booster The booster doubles or triples a voltage input to the Vci pin. With this function, both the internal logic units and LCD drivers can be controlled with a single power supply. Oscillator The HD66717 can provide R-C oscillation simply ...
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HD66717 Table 5 Relation between Character Codes and Character Patterns (ROM code: A03) Upper 0000 0001 0010 0011 0100 0101 0110 0111 bits Lower bits CG xxxx 0000 RAM (1) CG xxxx 0001 RAM (2) CG xxxx 0010 RAM (3) ...
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HD66717 Table 6 Relation between Character Codes and Character Patterns (ROM code: A13) Upper Lower bits 0000 0001 0010 0011 0100 0101 0110 0111 bits CG xxxx 0000 RAM (1) CG xxxx 0001 RAM (2) CG xxxx 0010 RAM (3) ...
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Modifying Character Patterns Character pattern development procedure The following operations correspond to the numbers listed in Figure 3: a. Determine the correspondence between character codes and character patterns. b. Create a listing indicating the correspondence between EPROM addresses and data. ...
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HD66717 Hitachi Computer processing Create character pattern listing Evaluate character patterns No Art work Masking Sample Sample evaluation production Figure 3 Character Pattern Development Procedure 472 User Start Determine character patterns Create EPROM 5 address data listing Write EPROM EPROM ...
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Programming Character Patterns This section explains the correspondence between addresses and data used to program character patterns in EPROM. Programming to EPROM The HD66717 character generator ROM can generate 240 5 correspondence between the EPROM address data and the character ...
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HD66717 Table 8 Example of Relationships between Character Code (DDRAM) and Character Pattern (CGRAM Data) Character code (DDRAM data ...
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Table 9 Correspondence between Segment Display SEGRAM Addresses (ASEG) and Driver Signals ASEG Address MSB LSB ...
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HD66717 Table 10 Correspondence between Annunciator Display Addresses (AAN) and Driver Signals AAN Address MSB LSB ASEG1 ASEG1 Blink Data ASEG5 ASEG5 Blink Data ASEG9 ASEG9 ...
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Instructions Outline Only the instruction register (IR) and the data register (DR) of the HD66717 can be controlled by the MPU. Before starting internal operation of the HD66717, control information is temporarily stored in these registers to allow interfacing with ...
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HD66717 Instruction Description Status Read The status read instruction (Figure 4) reads the busy flag (BF) indicating that the system is now internally operating on a previously received instruction the internal operation is in progress. The ...
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Return Home The return home instruction (Figure 6) sets DDRAM address 0 into the address counter. The DDRAM contents do not change.The cursor or blinking goes to the top left of the display. Start Oscillator The start oscillator instruction (Figure ...
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HD66717 Cursor Control The cursor control (Figure 9) includes the B/W, C, and B bits. B/W: When B the character at the cursor position is cyclically (every 32 frames) displayed with black-white inversion. C: The cursor is displayed ...
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Display On/Off Control The display on/off control instruction (Figure 11) includes DC, DS, and LC bits. DC: The character display is on when and off when When off, the display data remains in DDRAM, ...
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HD66717 Power Control The cursor control instruction (Figure 12) includes the AMP, SLP, and STB bits. AMP: When AMP = 1, each voltage-follower for pins and the booster are turned on. When AMP = 0, current consumption ...
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Display Control The display control instruction (Figure 13) includes the NL and DL bits. NL1, NL0: Designates the number of display lines. This value determines the LCD drive multiplexing duty ratio (Table 11). The address assignment is the same for ...
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HD66717 Contrast Control The contrast control instruction (Figure 14) includes the SN and CT bits. SN2: Combined with the SN1 and SN0 bits described in the Scroll Control section to select the first line to be scrolled (display-start line). CT3–CT0: ...
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Scroll Control The scroll control instruction (Figure 16) includes the SN and SL bits. SN1, SN0: Combined with the SN2 bit described in the Contrast Control section to select the top line to be displayed (display-start line) through the data ...
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HD66717 SL2–SL0: Selects the top raster-row to be displayed (display-start raster-row) in the display-start line specified by SN2 to SN0. Any raster-row from the first to eighth can be selected (Table 14). This function is used to perform vertical smooth ...
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Annunciator/SEGRAM Address Set The annunciator/SEGRAM address set instruction (Figure 17) includes the DA and A bits. DA: Turns annunciator display on or off. When annunciator display is turned on and driven statically. When annunciator ...
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HD66717 CGRAM Address Set The CGRAM address set instruction (Figure 18) includes the A bits. AAAAA: Used for setting the CGRAM address in the address counter (AC). The CGRAM addresses range from 00H to 1FH (32 addresses) (Table 15). Once ...
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DDRAM Address Set The DDRAM address set instruction (Figure 19) includes the A bits. AAAAAAA: Used for setting the DDRAM address in the address counter (AC). The DDRAM addresses range from 00H to 4BH (60 addresses) (Table 16). Once the ...
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HD66717 Write Data to RAM The write data to RAM instruction (Figure 20) writes 8-bit data to annunciator or DDRAM, or lower 5-bit data to SEGRAM or CGRAM that is selected by the previous specification of the address set instruction ...
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Table 17 Instruction List Instruction No. R/W RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Description Status Clear display Return home Start OS 0 ...
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HD66717 Table 17 Instruction List (cont) Instruction No. R/W RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Description Write data RAM Read data from RAM Internally operating I/D = ...
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Reset Function Initializing by Internal Reset Circuit The HD66717 is internally initialized by RESET input. During reset, the system executes the instructions as described below. Here, the busy flag (BF) therefore indicates a busy state (BF = 1), accepting no ...
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HD66717 k. Annunciator control Annunciator display off 2. RAM data initialization a. DDRAM All addresses are initialized to 20H by the clear display instruction b. CGRAM/SEGRAM Not automatically initialized by reset input; must be initialized by software ...
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Transferring Serial Data Bus Interface Grounding the IM1 and IM0 pins (interface mode pins) allows serial data transfer conforming to the I bus interface over the serial data line (SDA) and serial transfer clock line (SCL). Here, ...
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HD66717 2 Table 18 First Bytes Bus Interface Data First Byte S Bit 1 Bit bus system Transfer start A6 A5 HD66717 Transfer start ID5 ID4 O I Transfer start ...
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Clock-Synchronized Serial Interface Setting the IM1 and IM0 pins (interface mode pins) to the GND and high levels, respectively, allows standard clock-synchronized serial data transfer, using the chip select (CS*), SDA, and SCL lines. Here, the HD66717 exclusively receives data. ...
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HD66717 Transfer start CS* (Input SCL (Input) SDA ID5 ID4 ID3 ID2 ID1 ID0 RS (Input) Device ID code Start byte CS* (Input SCL (Input) SDA ...
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Transferring Parallel Data Interface with an 8-Bit MPU Eight-bit data can be transferred in parallel by setting the IM1 and IM0 pins to the V respectively (Figure 24). The HD66717 can interface directly with an 8-bit bus synchronized with the ...
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HD66717 Interface with a 4-Bit MPU Four-bit data can be transferred in parallel by setting both the IM1 and IM0 pins to the V 26). Four-bit data representing higher or lower bits of 8-bit instructions or 8-bit RAM data can ...
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Oscillator Circuit The HD66717 can either be supplied with operating clock pulses externally (external clock mode) or oscillate using an internal R-C oscillator and an external oscillator-resistor (internal oscillation mode), as shown in Figure 28. An appropriate oscillator-resistor must be ...
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HD66717 1-line selection period COM1 COM2 COMS2 COMS1 V4 V5 Figure 29 LCD Drive Output Waveform Example (4-line display ...
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Power Supply for Liquid Crystal Display Drive When External Power Supply and Internal Operational Amplifiers are Used To supply LCD drive voltage directly from the external power supply without using the internal booster, circuits should be connected as shown in ...
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HD66717 OPOFF = GND AGND GND 4-line display with 1/6 bias OPOFF = GND ...
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When an Internal Booster and Internal Operational Amplifiers are Used To supply LCD drive voltage using the internal booster, circuits should be connected as shown in Figure 31. Here, contrast can be adjusted through the CT bits of the contrast-control ...
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HD66717 Figure 32 Temperature Compensation Circuit Example 506 HD66717 Vci Thermistor Tr GND ...
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The HD66717’s internal operational amplifiers have a reduced drive current to save current consumption; when the internal operational amplifiers cannot fully drive the LCD panel used, an appropriate capacitors must be inserted between each output of V1OUT to V5OUT and ...
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HD66717 When an Internal Booster and External Bleeder-Resistors are Used When the internal operational amplifiers cannot fully drive the LCD panel used voltages can be supplied through external bleeder-resistors (Figure 34). Here, the OPOFF pin must be ...
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Contrast Adjuster Multiplexing Drive System Contrast for an LCD controlled by the multiplexing drive method can be adjusted by varying the liquid- crystal drive voltage (potential difference between V instruction (electron volume function). See Figure 35 and Table 20. The ...
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HD66717 Table 20 Contrast-Adjust Bits (CT) and Variable Resistor Values CT Register CT3 CT2 CT1 ...
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LCD Module Interface Segment data output pins SEG1 to SEG60 can be connected either from left to right or right to left of an LCD panel according to the SFT pin level. When the SFT pin is grounded, SEG1 is ...
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HD66717 a) 12-character x 3-line display (SEG line above the panel : SFT = GND) SEG60 SEG59–2 SEG1 COMS1 COM1 – SFT COM8 GND COM9 – COM16 COM17 – COM24 COMS2 MODE 2ndF Clock ON ACOM ASEG1– ASEG10 b) 12-character ...
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Segment Display and Annunciator Display The HD66717 provides both segment display, which is driven by the multiplexing method, and annunciator display, which is driven statically. Annunciator display is driven at a logic operating voltage (V – AGND) and is thus ...
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HD66717 Table 22 Correspondence between Segment Display SEGRAM Addresses (ASEG) and Driver Signals ASEG Address Common MSB LSB Signal COMS1 COMS1 COMS1 COMS1 1 ...
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Annunciator Drive Figure 37 shows annunciator drive output waveforms in two modes. i) Normal mode and sleep mode V level CC ACOM V level CC ASEG1 V level CC ASEG2 ii) Standby mode (without oscillation) V level CC EXM (Input) ...
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HD66717 Vertical Smooth Scroll The HD66717 can scroll in the vertical direction in units of raster-rows. This function is achieved by writing character codes into the DDRAM area that is not being used for display. In other words, since the ...
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Set initial data to all DDRAM addresses 1) Not scrolled · SN2–0 = 000 · SL2–0 = 000 2) 1 raster-row scrolled up · SL2–0 = 001 3) 2 raster-row scrolled up · SL2–0 = 010 4) 3 raster-row scrolled ...
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HD66717 Set initial data to all DDRAM addresses 1) Not scrolled · SN2–0 = 000 · SL2–0 = 000 2) 1 raster-row scrolled up · SL2–0 = 001 3) 2 raster-row scrolled up · SL2–0 = 010 4) 3 raster-row ...
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Line-Cursor Display The HD66717 can assign a cursor attribute to an entire line corresponding to the address counter value by setting the LC bit to 1 (Table 24). One of three line-cursor modes can be selected: a black-white inverting blink ...
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HD66717 Figure 40 Example of Black-White Inverting Blink Cursor ( B 520 Alternates every 32 frames ...
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Figure 41 Example of Underline Cursor ( HD66717 521 ...
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HD66717 Figure 42 Example of Blink Cursor ( 522 Alternates every 32 frames ...
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Double-Height Display The HD66717 can double the height of any desired line from the first to third lines. A line can be selected by the DL3 to DL1 bits as listed in Table 25. All the standard font characters stored ...
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HD66717 i) 3-line display example (DL1 = 0, DL2 = 1) 1st line: normal display 2nd line: double-height display ii) 4-line display example ( DL2 = 0, DL3 = 0) 1st line: double-height display 2nd line: normal display ...
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Partial-Display-Off Function The HD66717 can program the number of display lines (NL1 and NL0 bits), divide the internal operating frequency by four (OSC bit), and adjust the display contrast (CT bit). Combining these functions, the HD66717 can turn off the ...
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HD66717 Figure 44 Example of Partially-Off Display (date and time indicated) 526 Display available (driven with selection level) Display available (driven with selection level) Display unavailable (driven with deselection level) ...
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Sleep Mode Setting the sleep mode bit (SLP puts the HD66717 in sleep mode, where the device halts all the internal display operations except for annunciator display operations, thus reducing current consumption. Specifically, character and segment displays, which ...
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HD66717 Standby Mode Setting the standby mode bit (STB puts the HD66717 in standby mode, where the device stops completely, halting all internal operations including the R-C oscillator, thus further reducing current consumption compared to that in sleep ...
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Absolute Maximum Ratings* Item Symbol Power supply voltage ( Power supply voltage (2) V – Input voltage Vt Operating temperature T opr Storage temperature T stg Note the LSI is used above these absolute ...
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HD66717 DC Characteristics (V = 2.4V to 5.5V Item Symbol Min Input high voltage VIH 0.7V Input low voltage VIL –0.3 –0.3 Output high voltage VOH1 0.75V (1) (DB0–DB7 pins) Output low voltage (1) VOL1 — (DB0–DB7 pins) ...
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Booster Characteristics Item Symbol Min Output voltage VUP2 8.0 (V5OUT2 pin) Output voltage VUP3 7.0 (V5OUT3 pin) Input voltage VCi 1.0 Note: * Refer to the Electrical Characteristics Notes section following these tables. Typ Max Unit Test Condition 8.8 — ...
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HD66717 AC Characteristics (V = 2.4V to 5.5V Clock Characteristics (V = 2.4V to 5.5V) CC Item External External clock frequency clock External clock duty ratio operation External clock rise time External clock fall time R Clock oscillation ...
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Write Bus Interface Timing Characteristics without Read Operation (V Item Enable cycle time Enable pulse width V = 2 (“High” level 3 Enable rise/fall time Address set-up time (RS, R/W ...
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HD66717 I2C bus Interface Operation (V = 4.5V to 5.5V) CC Item Symbol SCL clock cycle time t SCL clock high-level width t SCL clock low-level width t SCL/SDA rise/fall time t Bus free time t Start hold time t ...
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Electrical Characteristics Notes 1. All voltage values are referred to GND = 0V. If the LSI is used above the absolute maximum ratings, it may become permanently damaged. Using the LSI within the given electrical characteristic is strongly recommended to ...
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HD66717 6. The TEST pin must be grounded and the ID5 to ID0, IM1, IM0, SFT, EXM, and OPOFF pins must be grounded or connected Applies to the ACK bit for I C bus ...
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Applies to the internal oscillator operations using oscillation resistor R OSC1 R f OSC2 Referential data 200 160 150 100 50 0 150 100 200 15. Booster characteristics test circuits are shown in Figure 50. ( Double boosting ) ...
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HD66717 Referential data VUP2 = V – V5OUT2 VUP3 = V CC (i) Relationship between the obtained voltage and input voltage Double boosting 2.0 3.0 Vci (V) Vci = V , fcp ...
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Relationship between the obtained voltage and the load current. Double boosting 9.0 8.5 8.0 7.5 7.0 6.5 6.0 0.0 0.5 1.0 I (mA) O Vci = V = 4.5V 180 Load ...
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HD66717 Timing Characteristics R/W E DB0 – DB7 Figure 52 Bus Write Operation R/W E DB0 – DB7 Figure 53 Bus Read Operation 540 ...
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Start : S CS* VIL t t CSU scr VIH SCL VIL t SISU VIH SDA Valid data VIL Figure 54 Clock-Synchronized Serial Interface Timing Start :S Stop : P VIH VIH VIH SDA VIL VIL t t SDAH BUP ...
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HD66717 RESET* VIL 542 t RES Figure 56 Reset Timing VIL ...