AX88655P ASIX [ASIX Electronics Corporation], AX88655P Datasheet
AX88655P
Related parts for AX88655P
AX88655P Summary of contents
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Gigabit Ethernet Switch with Embedded Memory Features 5-Port Gigabit Ethernet switch integrating MACs, packet buffer memory and switching engine with GMII/MII interface Full Duplex 1000 Mbit/s. Full and Half Duplex 10/100 Mbit/s Supports auto-sensing or manual selection for speed ...
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... System Block Diagram AX88655P Switch Controller 5 * 10/100/1000 Mbps PHYs AX88655 P 5-Port 10/100/1000BASE-T Ethernet Switch EEPROM 2 ASIX ELECTRONICS CORPORATION ...
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AX88655 OVERVIEW 1 ENERAL ESCRIPTION 1.2 AX88655 B LOCK 1 ONNECTION 2.0 I/O DEFINITION ............................................................................................................................................... 8 2.1 GMII/MII I NTERFACE 2.1.1 GMII Interface Port 0 ................................................................................................................................ 8 2.1.2 GMII Interface Port 1 ................................................................................................................................ ...
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ELECTRICAL SPECIFICATION AND TIMING 5 BSOLUTE AXIMUM 5 ENERAL PERATION 5 HARACTERISTICS 5.4 AC SPECIFICATIONS 5.4.1 X_IN Signal Timing.................................................................................................................................. 20 5.4.2 Reset Signal Timing ................................................................................................................................. 20 5.4.3 GMII Transmit/Receive Signals Timing.................................................................................................... 21 5.4.4 ...
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F -1 AX88655 LOCK F -2 AX88655 IAGRAM AX88655 P 5-Port 10/100/1000BASE-T Ethernet Switch FIGURES IAGRAM ........................................................................................................... 6 ................................................................................................................... 7 5 ASIX ELECTRONICS CORPORATION ...
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AX88655 Overview 1.1 General Description The AX88655 Gigabit switch controller supports five 10/100/1000 Mbps ports in wire-speed operation. The AX88655 Gigabit switch controller provides five 10/100/1000 Ethernet ports with GMII/MII interface. AX88655 supports GMII (802.3ab) interface with full-duplex operation ...
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... VSS 249 GTX_CLK0 250 VDD25 251 TX_CLK0 252 TXD0[0] 253 TXD0[1] 254 TXD0[2] 255 TXD0[3] 256 AX88655 P 5-Port 10/100/1000BASE-T Ethernet Switch AX88655P 10/100/1000Mbps Ethernet Switch Controller Fig-2 AX88655 Pin Diagram 7 128 127 126 125 124 123 122 121 120 119 118 ...
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Pin Descriptions 2.0 I/O Definition The following terms describe the AX88655 pin-out: All pin names with the “/” suffix are asserted low. The following abbreviations are used in following Tables. I Input O Output I/O Input/Output OD Open Drain ...
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GMII Interface Port 1 Signal Name I/O Pin No. GTX_CLK1 O TX_EN1 O TXD1[7: – 60 TX_CLK1 I/PD COL1 I/PD CRS1 I/PD RX_DV1 I RX_CLK1 I RXD1[7:0] I/ 2.1.3 GMII Interface Port 2 Signal ...
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GMII Interface Port 4 Signal Name I/O Pin No. GTX_CLK4 O TX_EN4 O TXD4[7:0] O 148 – 141 TX_CLK4 I/PD COL4 I/PD CRS4 I/PD RX_DV4 I RX_CLK4 I RXD4[7:0] I/PD 134 - 127 2.2 Miscellaneous Signal Name I/O Pin ...
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NC N 41, 15, 16, 17, 21, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 43, 167, 172, 173, 174, 175, 183, 184, 189, 190, 191, 192, 196, 198, 199, 200, 201, 202, 203, 204, 205, ...
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Functional Description 3.1 Introduction In general, the AX88655 device is a highly integrated Layer 2 switch. It supports five 10/100/1000 ports with on-chip MACs. It also supports integrated switching logic, packet queuing memory and packet storage memory. The AX88655 ...
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PHYs via MDIO/MDC interface after power on reset. The AX88655 will periodically and continuously poll and update the link status and link partner’s ability which include speed, duplex mode, and 802.3x flow control capable status of the connected ...
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Register Descriptions Registers Table Summary: Address Reserved PortPair1[7: PortPair3[7:0] LowQueueWeight[3:0] 0C ...
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R/W FlowCtrlEnable for MAC’s receive part of Port[4:0] are configured by internal 8051 0: not identify PAUSE frames by receive part of MAC 1: can identify PAUSE frames. That is, PauseTimer of MAC will be active. 7:5 Reserved R/W ...
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R/W All_Bit of PortPair #1 when QoS[0] is high 10:8 R/W Port_ID of PortPair #1 when QoS[0] is high 7 All_Bit of PortPair #0 when QoS[0] is high R/W 6:4 R/W Port_ID of PortPair #0 when QoS[0] is high ...
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R/W Back-off algorithm selection 0: disable. Device will perform the IEEE standard exponential back off algorithm when a collision occurs. 1: enable. When collisions occur, the MACs will back off slots stop generate JAM ...
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Register 11 BIT R/W 15:10 R/W Reserved LowWaterMarkForFlowCtrl. This is a ten-bit register containing unsigned integer for 9:0 R/W transmit queues whether generate PAUSE-ON or not. 4.19 Register 12 BIT R/W MaxJam. This is a six-bit register containing unsigned ...
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ELECTRICAL SPECIFICATION AND TIMING 5.1 Absolute Maximum Ratings Description Operating Temperature Storage Temperature Supply Voltage Input Voltage Output Voltage Lead Temperature (soldering 10 seconds maximum) Note: Stress above those listed under Absolute Maximum Ratings may cause permanent damage to ...
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AC specifications 5.4.1 X_IN Signal Timing X_IN Tr Symbol Description Tcyc CYCLE TIME Thigh CLK HIGH TIME Tlow CLK LOW TIME Tr/Tf CLK SLEW RATE 5.4.2 Reset Signal Timing SYSCLK /RST Symbol Description Trst Reset pulse width AX88655 P ...
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GMII Transmit/Receive Signals Timing T0 GTX_CLK TX_EN TXD[7:0] Symbol Description T0 GTX_CLK Clock Cycle Time T1 GTX_CLK Clock High Time T2 TX_EN and TXD data setup to GTX_CLK rising edge T3 TX_EN and TXD data hold from GTX_CLK rising ...
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Mbps MII Transmit/Receive Signals Timing T0 TX_CLK TX_EN T3 TXD[3:0] Symbol Description T0 TX_CLK Cycle Time T1 TX_CLK High Time T2 TX_CLK rising edge to TX_EN Delay T3 TX_CLK rising edge to TXD Delay T4 RX_CLK T6 RX_CRS ...
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Mbps MII Transmit/Receive Signals Timing T0 TX_CLK TX_EN T3 TXD[3:0] Symbol Description T0 TX_CLK Cycle Time T1 TX_CLK High Time T2 TX_CLK rising edge to TX_EN Delay T3 TX_CLK rising edge to TXD Delay T4 RX_CLK T6 RX_CRS ...
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AX88655 P 5-Port 10/100/1000BASE-T Ethernet Switch 24 ASIX ELECTRONICS CORPORATION ...
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PACKAGE INFORMATION pin 1 b SYMBOL AX88655 P 5-Port 10/100/1000BASE-T Ethernet Switch MILIMETER MIN. 0.25 0. ASIX ELECTRONICS CORPORATION A2 A1 NOM MAX 3.4 ...
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... Switch Controller 1 GMII PHY A.2 AX88655 as 5-Port Smart switch (DIP switch configurable) LEDs or General Serial Output via GPIO AX88655P Switch Controller 5 * 10/100/1000Mbps PHYs AX88655 P 5-Port 10/100/1000BASE-T Ethernet Switch AX88655P Quad GMII PHY Or 4 GMII PHYs Configuration Serial In via GPIO 26 I/O Port for Configuration From PC ...
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... A.3 AX88655 for 10/100Mbps Ethernet Backbone 5-port Gigabit switch WAN Router Using 2 Gigabit Ports Up-link and Trunking form a 12.8G Non-blocking backbone A.4 AX88655 for Super Server Trunking Application 5-port Gigabit switch AX88655 P 5-Port 10/100/1000BASE-T Ethernet Switch AX88655P Switch Controller 16*10/100Mbps +2*1000Mbps Ethernet Switch AX88655 P Switch Controller ...
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Appendix B: Design Note B.1 Using MII I/F connects to MAC Using MII interface to connect to MAC type device COL0 TX_EN0 TX_CLK0 TXD0[3:0] CRS0 RX_DV0 RX_CLK0 RXD0[3:0] AX88655 / Switch Note: 1. The MAC needs to run at full-duplex ...
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Appendix C: Weight Setting for QoS Service Ratio WeightForHighQue[3:0] (High : Low ...
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Demonstration Circuit (A) : AX88658 Smart Switch AX88655 P 5-Port 10/100/1000BASE-T Ethernet Switch Application. OSC_CKT 25M_P0 25M_P0 25M_P1 25M_P2 25M_P1 25M_P2 25M_P3 25M_P4 25M_P3 25M_P4 SYSCLK OSC_CKT VDD18_1 VDD25 PORT0 GPHY0 CRS0 CRS MDIO COL0 MDIO COL MDC RXD0[0..7] MDC ...
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GTX_CLK GTX_CLK TXD[0..7] TXD[0..7] TX_EN TX_EN MDIO MDIO MDC MDC RESET# PHY_RST# 25M_IN 25MHZ VDD25 VDD25 VDD18 VDD18 GND GND R10 4.7K RESET# COL 39 COL CRS 40 CRS GND R19 4.7K 41 RX_ER RXD[0..7] VDD_O 42 IO_VDD GND 43 ...
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GTX_CLK GTX_CLK TXD[0..7] TXD[0..7] TX_EN TX_EN MDIO MDIO MDC MDC RESET# PHY_RST# 25M_IN 25MHZ VDD25 VDD25 VDD18 VDD18 GND GND R52 4.7K RESET# COL 39 COL CRS 40 CRS GND R61 4.7K 41 RX_ER RXD[0..7] VDD_O 42 IO_VDD GND 43 ...
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GTX_CLK GTX_CLK TXD[0..7] TXD[0..7] TX_EN TX_EN MDIO MDIO MDC MDC RESET# PHY_RST# 25M_IN 25MHZ VDD25 VDD25 VDD18 VDD18 GND GND R94 4.7K RESET# COL 39 COL CRS 40 CRS GND R103 4.7K 41 RX_ER RXD[0..7] VDD_O 42 IO_VDD GND 43 ...
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GTX_CLK GTX_CLK TXD[0..7] TXD[0..7] TX_EN TX_EN MDIO MDIO MDC MDC RESET# PHY_RST# 25M_IN 25MHZ VDD25 VDD25 VDD18 VDD18 GND GND R136 4.7K RESET# COL 39 COL CRS 40 CRS GND R145 4.7K 41 RX_ER RXD[0..7] VDD_O 42 IO_VDD GND 43 ...
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GTX_CLK GTX_CLK TXD[0..7] TXD[0..7] TX_EN TX_EN MDIO MDIO MDC MDC RESET# PHY_RST# 25M_IN 25MHZ VDD25 VDD25 VDD18 VDD18 GND GND R178 4.7K RESET# COL 39 COL CRS 40 CRS GND R187 4.7K 41 RX_ER RXD[0..7] VDD_O 42 IO_VDD GND 43 ...
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CRS0 CRS0 COL0 COL0 RXD0[0..7] RXD0[0..7] RX_CLK0 RX_CLK0 RX_DV0 RX_DV0 TX_CLK0 TX_CLK0 CRS1 CRS1 COL1 COL1 RXD1[0..7] RXD1[0..7] RX_CLK1 RX_CLK1 RX_DV1 RX_DV1 TX_CLK1 TX_CLK1 CRS2 CRS2 COL2 COL2 RXD2[0..7] RXD2[0..7] RX_CLK2 RX_CLK2 RX_DV2 RX_RV2 TX_CLK2 TX_CLK2 CRS3 CRS3 COL3 COL3 ...
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VDD33 VDD33 GND GND U7 L21 OUT VDD33 8 VCC GND C349 C350 F.B. 0.1uF 0.1uF 125MHz U9 L23 OUT VDD33 8 VCC GND C351 C352 F.B. 0.1uF 0.1uF 90MHz U10 L24 OUT VDD33 8 VCC GND C355 C356 F.B. ...
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VDD33 VDD33 VDD25 VDD25 VDD25_2 VDD25_2 VDD18_2 VDD18_2 VDD18_1 VDD18_1 GND GND RST_CTL# RST_CTL# 5VSB 5V U12 R247 4.7K 3.3V 3. 3.3V 3. 3.3V -12V 3.3V R249 GND GND 13 3 GND GND PS_ON 14 4 ...
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VDD33 VDD33 GND GND SDIO SDIO SDC SDC R272 4.7K 14 U18C 9 INIT 74HC00 VDD33 U21 R279 VDD33 A0 VCC C426 R281 RST_CTL R282 SDC ...
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Revision history Revision Date V. 1.0 3/14/02 4F, NO.8, HSIN ANN RD., SCIENCE-BASED INDUSTRIAL PARK, HSINCHU, TAIWAN, R.O.C. TEL: 886-3-5799500 FAX: 886-3-5799558 Email: Web: Comment Initial release. support@asix.com.tw http://www.asix.com.tw 40 http://www.asix.com.tw ASIX Electronic ...