AX88850 ASIX [ASIX Electronics Corporation], AX88850 Datasheet
AX88850
Related parts for AX88850
AX88850 Summary of contents
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... No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product. ASIX ELECTRONICS CORPORATION 2F, NO.13, Industry East Rd. II, Science-based Industrial Park, Hsin-Chu City, Taiwan, R.O.C. TEL: 886-3-579-9500 100BASE-TX/FX Repeater Controller ASIX AX88850 100BASE-TX/FX Repeater Controller Data Sheet(11/03/’97) FAX: 886-3-579-9558 AX88850 ...
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... AX88850 1.0 AX88850 OVERVIEW ......................................................................................................................................... 5 1 ....................................................................................................................................... 5 ENERAL ESCRIPTION 1.2 F ............................................................................................................................................................ 6 EATURES 1 ................................................................................................................................................. 7 LOCK IAGRAM 1 ONNECTION IAGRAM FOR 1 ONNECTION IAGRAM FOR 1 ONNECTION IAGRAM FOR 1 ONNECTION IAGRAM FOR 2.0 PIN DESCRIPTION........................................................................................................................................... 12 2.1A PCS ............................................................................................................................................. 12 INTERFACE 2.1B MII ( INTERFACE SHARE BUS 2.2 MII ...
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... AX88850 5.0 ELECTRICAL SPECIFICATION AND TIMING ......................................................................................... 34 5 BSOLUTE AXIMUM ATINGS 5 ENERAL PERATION ONDITIONS 5 ...................................................................................................................................... 34 HARACTERISTICS 5.4 AC ........................................................................................................................................... 35 SPECIFICATIONS 5.4.1 MII Interface Timing Tx & Rx................................................................................................................... 35 5.4.2 Station Management ................................................................................................................................. 36 5.4.3 PCS Interface Timing................................................................................................................................. 37 5.4.4 LED DISPLAY ........................................................................................................................................... 37 5.4.5 LED Display After Reset ........................................................................................................................... 38 5.4.6 Repeater ID Daisy Chain........................................................................................................................... 38 5.4.7 Expansion Bus............................................................................................................................................ 39 6.0 PACKAGE INFORMATION............................................................................................................................ 40 ...
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... AX88850 (PCS IG HIP LOCK IAGRAM (MII IG HIP LOCK IAGRAM ONNECTION IAGRAM FOR ONNECTION IAGRAM FOR ONNECTION IAGRAM FOR ONNECTION IAGRAM FOR FIGURES -- 8 PCS + 2 MII)..................................................................... 7 MODE CONFIGURATION -- 16 MII + 2 MII) ...
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... The AX88850 Repeater Controller is a subset of a repeater set containing all the repeater-specific components and functions, exclusive of PHY components and functions. The AX88850 family has two kind of interfaces to connect to PHY devices. There are Physical coding sub-layer (PCS) interface and Media Independent Interface (MII). ...
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... Power on LED diagnosis. All the LED display will follow the “ON-OFF-ON-OFF- Normal” operation procedure during/after power on reset. Dedicated collision LED display 208-pin PQFP The AX88850 Family has the following members: AX88851 16 shared MII ports + 2 dedicated MII ports AX88852 ...
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... AX88850 1.3 Block Diagram & ili ...
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... AX88850 1.4 Pin Connection Diagram for AX88851 (16MII + 2MII mode < 0 > < 1 > < 2 > < 3 > ...
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... AX88850 1.5 Pin Connection Diagram for AX88852 (8MII + 2MII mode < 0 > < 1 > < 2 > < 3 > ...
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... AX88850 1.6 Pin Connection Diagram for AX88853 (8PCS + 2MII mode < 0 > < 1 > < 2 > < 3 > ...
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... AX88850 1.7 Pin Connection Diagram for AX88854 (Management mode < 0 > < 1 > < 2 > < 3 > ...
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... AX88850 2.0 Pin Description 2.1A PCS interface Signal Name Type Pin No. RDATA[0][4:0] I/PU 181-177, RDATA[1][4:0] I/PD* 195-191 RDATA[2][4:0] I/PD* 208-204 RDATA[3][4:0] I/PD* 14-10 RDATA[4][4:0] I/PD* 30,29,26- 24 RDATA[5][4:0] I/PD* 44-40 RDATA[6][4:0] I/PD* 57-53 RDATA[7][4:0] I/PU 70-66 RSCLK[0] I 182 RSCLK[1] I 196 RSCLK[ RSCLK[ RSCLK[ RSCLK[ RSCLK[ RSCLK[ RSD[0] I /PD 183 RSD[1] I/PD 197 ...
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... AX88850 2.1B MII interface (share bus MII group 0 port & MII group 1 port MII group MII group 1 Signal Name Type Pin No. M0_TX_ER O/ML 22 M1_TX_ER O/ML 38 M0_TXD[3:0] O/H 21-18 M1_TXD[3:0] O/H 37-34 M0_TX_EN[7:0] O/L 4,3,203, 202, 189-186 M1_TX_EN[7:0] O/L 74,65-63, 50-47 M0_RXD[3:0] I/PU 13-10 M1_RXD[3:0] I/PU 29,26-24 M0_RX_ER I/PD 14 M1_RX_ER I/PD 30 M0_RX_CLK I 15 M1_RX_CLK I 31 M0_RX_DV I/PD 16 M1_RX_DV I/PD 32 M0_CRS[7:0] ...
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... AX88850 2.2 MII interface ( two individual MII ports ) Signal Name Type Pin No. TX_ER O/ML 92 (share) TXD[3:0] O/ML 97-94 (share) TX_EN[0] O/L 82 TX_EN[1] O/L 98 RXD[0][3:0] I/PU 86-83 RXD[1][3:0] I/PU 102-99 RX_ER[0] I/PD 87 RX_ER[1] I/PD 104 RX_CLK[ RX_CLK[1] I 105 RX_DV[0] I/PD 89 RX_DV[1] I/PD 106 CRS[0] I/PD 90 CRS[1] I/PD 107 COL O/ML 91 (share) OPT0 I/PU 81 OPT1 I/PU 108 Description Transmit Error : TX_ER is transition synchronously with respect to the rising edge of TX_CLK ...
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... Station Management Data Direction : Direction signal for an external bi- directional buffer on the MDIO signal MDIO data flows into the AX88850 1 = MDIO data flows out of the AX88850 Defaults to 0 when no register access is present. Buffered Station Management Data Clock : Buffered MDC signal. Allow more devices to be chained on the MII serial bus. ...
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... Description the “active” AX88850 to all other “inactive” AX88850s. The bus-master of the IRD bus is determined by IR_VECT bus arbitration. INTER REPEATER DATA ERROR: This signal reflect the RX_ER status of the active port across the inter repeater bus. Used to track receive errors from the PHY in real time ...
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... AX88850 2.6 LED Display Signal Name Type Pin No. LED[7:0] O/L 125-122, 120-117 LED_SYN O/L 126 /COLLED O/MH 127 Description LED Display Information : Those signals indicate each port‘s Partition, Jabber, Link/Activity, Utilization % (global), Collision % (global) in sequence. For detail , see the LED timing specification The Utilization % display define as following : ...
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... AX88850 2.7 Miscellaneous Signal Name Type Pin No. LCLK or I 168 TX_CLK /RST I 165 RST_DLY O/L 135 DAISY_IN I/PU 133 DAISY_OUT O/L 134 TEST I/PD 166 GEP[3:0] I/O/L 175-172 General Purpose I/O Pins : Those pins just for system application usage. I.e. /PU MEDIA I/PD 130 OPTION I/PU 129 VDD I 1,17,27, 33,52,73, 80,103, 128,132, 156,171, 184 ...
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... AX88850 3.0 Functional Description 3.1 PCS interface logic The PCS logic performs PCS / MII receiving / transmitting interface. When it receives, first deciphers the signals from RDATA<4:0>, then do symbol alignment after detecting /J/K/ codes, then data is aligned to do 5B/4B decoding. When it transmits, first do 4B/5B encoding to convert MII signals to PCS signals, then enciphers and send to TDATA< ...
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... To prevent an illegally long reception of data from reaching the repeater unit, each port has its own jabber timer reception exceeds this duration(64K bit times for AX88850), the jabber condition will be detected. In this condition, repeater unit will disable receive and transmit packets for the jabbered port and the other ports remain the normal operation ...
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... Two signals of /IR_ACTO[7:0] are low in collision state corresponding to different RPTR_ID[2:0]. 3.7 Management Logic AX88850 provides the required management information associated with a packet for management chip which statistics processed on a per packet basis. Transmit ready signal TX_RDY is used as a framing signal for management data MD ...
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... These counters can be read out by MIB serial access interface and will be clear after read operation. 3.9 Station Management Access Interface The AX88850 provides 128 registers held in 4 pages of 32(Page Register).These registers are 16 bits wide. Only one register of one page can be access at the same time through the MII serial reset, Page 0 Register is the default setting ...
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... AX88850 DAISY_IN/OUT frame format idle start bit 1 0 Notes: PARITY = 1 when sum of 1‘s in RID[2:0] is even There are two flag : /DIS_DAISY and /TO_ID_CLR which control daisy-chain access. If disable daisy-chain input (/DIS_DAISY = 0), the RID of current chip can‘t be override and don‘t care the present data on DAISY_IN daisy-chain input, the RID of current chip can be clear to 0 during time out period with the setting of /TO_ID_CLR = 0 ...
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... AX88850 3.11 LED Interface AX88850 provides per-port LED status indication for partition, jabber, link/activity and support rate-based LED for global utilization (%) and global collision frequency (%). Detail function is described on previous pin description (LED interface). LED[7:0] are all active low. 3.11.1 LED Status Driver wave-form for AX88851 ...
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... AX88850 3.11.2 LED Status Driver wave-form for AX88852 LED_SYN LED[ LED[ LED[ LED[ LED[ LED[ LED[ LED[ 3.11.3 LED Status Driver wave-form for AX88853 ...
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... AX88850 3.11.4 LED Status Driver wave-form for AX88854 LED_SYN L0/ LED[ L1/ LED[ L2/ L8/ LED[ L3/ L9/ LED[ L4/ LED[ L5/ LED[ ...
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... AX88850 4.0 REGISTERS The AX88850 has 128 16-bit registers which are separated into four pages with each page 32 words. At power-on or reset , the default value is page 0 registers. The register page can be changed by writing to the register address 1 on all the four pages . 4.1 Page 0 Register MAP ...
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... P13-SE … R/W Port 13 management counters ( as per ports 8,9 as above ) P13-PART 4.4 Page 3 Register MAP Address (hex) Name Access 0 CONFIG R/W Set AX88850 configuration ( same as page PAGE R/W Selects register from page 0 to page 3.. ( same as page 1 ) 2-F 10-13 P14-SE … R/W Port 14 management counters ( as per ports 8,9 as above ) P14-PART 14-17 P15-SE … ...
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... R/W Reset Repeater State Machines : Setting the bit holds the RSM in reset. The management event flags and counters are unaffected by this bit. Setting this bit while a reception is in progress may truncate the packet AX88850 in normal operation (default AX88850 held in reset . Access R/W D11-D8 : GEP I/O control. Default = 0h for input mode. Otherwise, =1h, enable output. ...
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... AX88850 4.7 Partition Status Register (PARTITION) Page 0 Address 2h Bit Bit Name D15-D10 Reserved D9-D0 PART[9: 0] Page 1 Address 2h Bit Bit Name D15-D8 Reserved D7-D0 PART[17: 10] 4.8 Jabber Status Register (JABBER) Page 0 Address 3h Bit Bit Name D15-D10 Reserved D9-D0 JAB[9: 0] Page 1 Address 3h Bit Bit Name D15-D8 Reserved D7-D0 JAB[17: 10] 4 ...
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... AX88850 4.10 Device ID Register (DEVICEID) Page 0 Address 5h Bit Bit Name D15-D13 Temp D12-D8 PORT_NUM D7 /IR_ACT_EN D6 /TO_ID_CLR D5 /DIS_DAISY D4-D0 RPTR_ID * Note : Host can’t override these signals. 4.11 Silicon Revision Register Page 1 Address 5h Bit Bit Name D15-D0 SI_REV[15:0] Access R/W Temporary Registers : reserved for system programer used. ...
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... AX88850 4.12 Port Management Counter Registers Each of the 18 ports of the AX88850 has a set of 4 event counters whose values can be read or pre-set (written) through the Port Management Counter Registers. When PCS (symbol) mode is selected, there is a set of false carrier counter / per port build-in on the chip. As for MII mode , the false carrier counter will be available on PHY, note that some PHY chip manufacturer not support those functions ...
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... AX88850 5.0 ELECTRICAL SPECIFICATION AND TIMING 5.1 Absolute Maximum Ratings Description Operating Temperature Storage Temperature Supply Voltage Input Voltage Output Voltage Lead Temperature (soldering 10 seconds maximum) Note : Stress above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to Absolute Maximum Ratings conditions for extended period, adversely affect device life and reliability 5 ...
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... AX88850 5.4 AC specifications 5.4.1 MII Interface Timing Tx & LCLK TX_EN (MTX_RDY) TX_ER TXD Symbol Description T0 Local Clock Cycle Time T1 Local Clock High Time T2 TX_EN or MTX_RDY Delay from LCLK High T3 TX_ER or TXD Delay from LCLK High T4 RX_CLK CRS T6 RXE T8 RXDV RXD RXER T1 T2 ...
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... AX88850 Symbol Description T4 RX_CLK Clock Cycle Time T5 RX_CLK Clock High Time T6 CRS to RXE Assertion Delay T7 CRS to RXE De-assertion Delay T8 CRS to RXDV Delay Requirement T9 RXD or RXDV setup to RX_CLK rise time 5.4.2 Station Management T1 T2 SMDC T3 T4 SMDIO Write Write T6 /SMDV SMDIR T8 BSMDC BSMDIO ...
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... AX88850 5.4.3 PCS Interface Timing TX LCLK TDATA RX RSCLK T3 RDATA Symbol Description T0 TDATA Valid From LCLK High T1 RSCLK Clock Cycle Time T2 RSCLK Clock High Time T3 RDATA Setup Time T4 RDATA Hold Time 5.4.4 LED DISPLAY LCLK T1 LED[7:0 D15 LED-SYN Symbol Description T1 LED Valid from LCLK Low ...
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... AX88850 5.4.5 LED Display After Reset /Reset T1 LED[7:0] LED_SYN ………………………………… Symbol Description T1 Repeater reset time T2 LED Blink Time After Reset T3 LED Dark Time Before Normal Display 5.4.6 Repeater ID Daisy Chain T2 T2 ...
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... AX88850 5.4.7 Expansion Bus CRS T1 IRD-ODIR IRD_CK IRD[3:0] /IRD_ER /IRD_V MD Symbol T1 CRS Assertion to IRD-ODIR Assertion T2 CRS De-Assertion to IRD-ODIR De-Assertion T3 IRD[3:0] Setup Time to IRD-CK High T4 /IRD_ER Setup Time to IRD-CK High T5 /IRD_V Setup Time to IRD-CK High T6 /IRD_V Hold Time from IRD-CK High T7 MD Setup Time to IRD-CK High ...
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... AX88850 6.0 PACKAGE INFORMATION pin 1 b SYMBOL MILIMETER MIN. 0.05 3.17 0.10 27.90 27.90 30.35 30.35 0. ASIX ELECTRONICS CORPORATION PRELIMINARY NOM MAX 0.25 0.5 3.32 3.47 0.20 0.30 28.00 28.10 28.00 28.10 0.50 30.60 30.85 30.60 30.85 0.60 0.75 1.30 10 ...