S9S12GN32F0CLF Freescale Semiconductor, S9S12GN32F0CLF Datasheet - Page 1134

• Manufacturer Part Number: S9S12GN32F0CLF
• Description: 16-bit Microcontrollers - MCU 16-bit,32k Flash 2k RAM
• Manufacturer: Freescale Semiconductor

Specifications of S9S12GN32F0CLF

• Rohs: yes
• Core: S12
• Processor Series: MC9S12G
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 1 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT

192 KByte Flash Module (S12FTMRG192K2V1)
reprogrammed to the unsecure state, if desired. In the unsecure state, the user has full control of the
contents of the backdoor keys by programming addresses 0x3_FF00-0x3_FF07 in the Flash configuration
field.
30.5.2
A secured MCU can be unsecured in special single chip mode by using the following method to erase the
P-Flash and EEPROM memory:
If the P-Flash and EEPROM memory are verified as erased, the MCU will be unsecured. All BDM
commands will now be enabled and the Flash security byte may be programmed to the unsecure state by
continuing with the following steps:
30.5.3
The availability of Flash module commands depends on the MCU operating mode and security state as
shown in
30.6
On each system reset the flash module executes an initialization sequence which establishes initial values
for the Flash Block Configuration Parameters, the FPROT and EEPROT protection registers, and the FOPT
and FSEC registers. The initialization routine reverts to built-in default values that leave the module in a
fully protected and secured state if errors are encountered during execution of the reset sequence. If a
double bit fault is detected during the reset sequence, both MGSTAT bits in the FSTAT register will be set.
CCIF is cleared throughout the initialization sequence. The Flash module holds off all CPU access for a
portion of the initialization sequence. Flash reads are allowed once the hold is removed. Completion of the
initialization sequence is marked by setting CCIF high which enables user commands.
1136
1. Reset the MCU into special single chip mode
2. Delay while the BDM executes the Erase Verify All Blocks command write sequence to check if
3. Send BDM commands to disable protection in the P-Flash and EEPROM memory
4. Execute the Erase All Blocks command write sequence to erase the P-Flash and EEPROM
5. After the CCIF flag sets to indicate that the Erase All Blocks operation has completed, reset the
6. Delay while the BDM executes the Erase Verify All Blocks command write sequence to verify that
7. Send BDM commands to execute the Program P-Flash command write sequence to program the
8. Reset the MCU
the P-Flash and EEPROM memories are erased
memory. Alternatively the Unsecure Flash command can be executed, if so the steps 5 and 6 below
are skeeped.
MCU into special single chip mode
the P-Flash and EEPROM memory are erased
Flash security byte to the unsecured state
Table
Initialization
Unsecuring the MCU in Special Single Chip Mode using BDM
Mode and Security Effects on Flash Command Availability
30-27.
MC9S12G Family Reference Manual,
Rev.1.23
Freescale Semiconductor