S9S12GN32F0CLF Freescale Semiconductor, S9S12GN32F0CLF Datasheet - Page 389

• Manufacturer Part Number: S9S12GN32F0CLF
• Description: 16-bit Microcontrollers - MCU 16-bit,32k Flash 2k RAM
• Manufacturer: Freescale Semiconductor

Specifications of S9S12GN32F0CLF

• Rohs: yes
• Core: S12
• Processor Series: MC9S12G
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 1 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT

10.3.2.14 Autonomous Periodical Interrupt Control Register (CPMUAPICTL)
The CPMUAPICTL register allows the configuration of the autonomous periodical interrupt features.
Read: Anytime
Write: Anytime
Freescale Semiconductor
0x02F2
APICLK
Reset
APIES
APIEA
APIFE
Field
APIE
APIF
7
4
3
2
1
0
W
R
APICLK
Autonomous Periodical Interrupt Clock Select Bit — Selects the clock source for the API. Writable only if
APIFE = 0. APICLK cannot be changed if APIFE is set by the same write operation.
0 Autonomous Clock (ACLK) used as source.
1 Bus Clock used as source.
Autonomous Periodical Interrupt External Select Bit — Selects the waveform at the external pin
API_EXTCLK as shown in
0 If APIEA and APIFE are set, at the external pin API_EXTCLK periodic high pulses are visible at the end of
1 If APIEA and APIFE are set, at the external pin API_EXTCLK a clock is visible with 2 times the selected API
Autonomous Periodical Interrupt External Access Enable Bit — If set, the waveform selected by bit APIES
can be accessed externally. See device level specification for connectivity.
0 Waveform selected by APIES can not be accessed externally.
1 Waveform selected by APIES can be accessed externally, if APIFE is set.
Autonomous Periodical Interrupt Feature Enable Bit — Enables the API feature and starts the API timer
when set.
0 Autonomous periodical interrupt is disabled.
1 Autonomous periodical interrupt is enabled and timer starts running.
Autonomous Periodical Interrupt Enable Bit
0 API interrupt request is disabled.
1 API interrupt will be requested whenever APIF is set.
Autonomous Periodical Interrupt Flag — After each time-out of the API (time-out rate is configured in the
CPMUAPIRH/L registers) the interrupt flag APIF is set to 1. This flag can only be cleared by writing a 1. Writing
a 0 has no effect. If enabled (APIE = 1), APIF causes an interrupt request.
0 API time-out has not yet occurred.
1 API time-out has occurred.
Figure 10-17. Autonomous Periodical Interrupt Control Register (CPMUAPICTL)
0
7
every selected period with the size of half of the minimum period (APIR=0x0000 in
Period.
= Unimplemented or Reserved
0
0
6
Table 10-16. CPMUAPICTL Field Descriptions
MC9S12G Family Reference Manual, Rev.1.23
Figure
0
0
5
10-18. See device level specification for connectivity of API_EXTCLK pin.
APIES
0
4
Description
S12 Clock, Reset and Power Management Unit (S12CPMU)
APIEA
0
3
APIFE
0
2
Table
APIE
0
1
10-20).
APIF
0
0
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