S9S12GN32F0CLF Freescale Semiconductor, S9S12GN32F0CLF Datasheet - Page 289

• Manufacturer Part Number: S9S12GN32F0CLF
• Description: 16-bit Microcontrollers - MCU 16-bit,32k Flash 2k RAM
• Manufacturer: Freescale Semiconductor

Specifications of S9S12GN32F0CLF

• Rohs: yes
• Core: S12
• Processor Series: MC9S12G
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 1 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT

7.1.3
A block diagram of the BDM is shown in
7.2
A single-wire interface pin called the background debug interface (BKGD) pin is used to communicate
with the BDM system. During reset, this pin is a mode select input which selects between normal and
special modes of operation. After reset, this pin becomes the dedicated serial interface pin for the
background debug mode. The communication rate of this pin is always the BDM clock frequency defined
at device level (refer to device overview section). When modifying the VCO clock please make sure that
the communication rate is adapted accordingly and a communication time-out (BDM soft reset) has
occurred.
7.3
7.3.1
Table 7-2
Freescale Semiconductor
System
Host
External Signal Description
Memory Map and Register Definition
shows the BDM memory map when BDM is active.
Block Diagram
Module Memory Map
Register Block
BKGD
BDMSTS
Register
BDMACT
ENBDM
UNSEC
TRACE
SDV
Interface
Serial
MC9S12G Family Reference Manual, Rev.1.23
Control
Data
Figure 7-1. BDM Block Diagram
Figure
Standard BDM Firmware
16-Bit Shift Register
Secured BDM Firmware
Instruction Code
LOOKUP TABLE
LOOKUP TABLE
7-1.
Execution
and
Background Debug Module (S12SBDMV1)
Bus Interface
Control Logic
and
Address
Data
Control
Clocks
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