S9S12GN32F0CLF Freescale Semiconductor, S9S12GN32F0CLF Datasheet - Page 54

• Manufacturer Part Number: S9S12GN32F0CLF
• Description: 16-bit Microcontrollers - MCU 16-bit,32k Flash 2k RAM
• Manufacturer: Freescale Semiconductor

Specifications of S9S12GN32F0CLF

• Rohs: yes
• Core: S12
• Processor Series: MC9S12G
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 1 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT

Device Overview MC9S12G-Family
1.7.2.3
The BKGD/MODC pin is used as a pseudo-open-drain pin for the background debug communication. It
is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MODC bit
at the rising edge of RESET. The BKGD pin has an internal pull-up device.
1.7.2.4
EXTAL and XTAL are the crystal driver and external clock signals. On reset all the device clocks are
derived from the internal reference clock. XTAL is the oscillator output.
1.7.2.5
PAD[15:0] are general-purpose input or output signals. These signals can have a pull-up or pull-down
device selected and enabled on per signal basis. Out of reset the pull devices are disabled.
1.7.2.6
PA[7:0] are general-purpose input or output signals. The signals can have pull-up devices, enabled by a
single control bit for this signal group. Out of reset the pull-up devices are disabled .
1.7.2.7
PB[7:0] are general-purpose input or output signals. The signals can have pull-up devices, enabled by a
single control bit for this signal group. Out of reset the pull-up devices are disabled .
1.7.2.8
PC[7:0] are general-purpose input or output signals. The signals can have pull-up devices, enabled by a
single control bit for this signal group. Out of reset the pull-up devices are disabled .
1.7.2.9
PD[7:0] are general-purpose input or output signals. The signals can have pull-up device, enabled by a
single control bit for this signal group. Out of reset the pull-up devices are disabled.
1.7.2.10
PE[1:0] are general-purpose input or output signals. The signals can have pull-down device, enabled by a
single control bit for this signal group. Out of reset the pull-down devices are enabled.
56
BKGD / MODC — Background Debug and Mode Pin
EXTAL, XTAL — Oscillator Signal
PAD[15:0] / KWAD[15:0] — Port AD Input Pins of ADC
PA[7:0] — Port A I/O Signals
PB[7:0] — Port B I/O Signals
PC[7:0] — Port C I/O Signals
PD[7:0] — Port D I/O Signals
PE[1:0] — Port E I/O Signals
The TEST pin must be tied to ground in all applications.
MC9S12G Family Reference Manual,
NOTE
Rev.1.23
Freescale Semiconductor