S9S12G48F0MLH Freescale Semiconductor, S9S12G48F0MLH Datasheet - Page 340

• Manufacturer Part Number: S9S12G48F0MLH
• Description: 16-bit Microcontrollers - MCU 16Bit 48KFlash 4096RAM MSCAN
• Manufacturer: Freescale Semiconductor

Specifications of S9S12G48F0MLH

• Rohs: yes
• Core: S12
• Processor Series: MC9S12G
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 48 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-64
• Mounting Style: SMD/SMT

S12S Debug Module (S12SDBGV2)
storage. The information bits indicate the size of access (word or byte) and the type of access (read or
write).
When tracing in Detail Mode, all cycles are traced except those when the CPU is either in a free or opcode
fetch cycle.
8.4.5.2.4
In Compressed Pure PC Mode, the PC addresses of all executed opcodes, including illegal opcodes are
stored. A compressed storage format is used to increase the effective depth of the trace buffer. This is
achieved by storing the lower order bits each time and using 2 information bits to indicate if a 64 byte
boundary has been crossed, in which case the full PC is stored.
Each Trace Buffer row consists of 2 information bits and 18 PC address bits
8.4.5.3
ADRH, ADRM, ADRL denote address high, middle and low byte respectively. The numerical suffix refers
to the tracing count. The information format for Loop1 and Normal modes is identical. In Detail mode, the
address and data for each entry are stored on consecutive lines, thus the maximum number of entries is 32.
In this case DBGCNT bits are incremented twice, once for the address line and once for the data line, on
each trace buffer entry. In Detail mode CINF comprises of R/W and size access information (CRW and
CSZ respectively).
Single byte data accesses in Detail Mode are always stored to the low byte of the trace buffer (DATAL)
and the high byte is cleared. When tracing word accesses, the byte at the lower address is always stored to
trace buffer byte1 and the byte at the higher address is stored to byte0.
342
Normal/Loop1
Detail Mode
Modes
Mode
Trace Buffer Organization (Normal, Loop1, Detail modes)
Compressed Pure PC Mode
When tracing is terminated using forced breakpoints, latency in breakpoint
generation means that opcodes following the opcode causing the breakpoint
can be stored to the trace buffer. The number of opcodes is dependent on
program flow. This can be avoided by using tagged breakpoints.
Number
Entry 1
Entry 2
Entry 1
Entry 2
Entry
Table 8-37. Trace Buffer Organization (Normal,Loop1,Detail modes)
CINF1,ADRH1
CINF2,ADRH2
Field 2
4-bits
PCH1
PCH2
MC9S12G Family Reference Manual, Rev.1.23
0
0
NOTE:
DATAH1
DATAH2
ADRM1
ADRM2
Field 1
PCM1
PCM2
8-bits
DATAL1
DATAL2
Field 0
ADRL1
ADRL2
8-bits
PCL1
PCL2
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