S9S12G48F0MLH Freescale Semiconductor, S9S12G48F0MLH Datasheet - Page 408

• Manufacturer Part Number: S9S12G48F0MLH
• Description: 16-bit Microcontrollers - MCU 16Bit 48KFlash 4096RAM MSCAN
• Manufacturer: Freescale Semiconductor

Specifications of S9S12G48F0MLH

• Rohs: yes
• Core: S12
• Processor Series: MC9S12G
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 48 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-64
• Mounting Style: SMD/SMT

S12 Clock, Reset and Power Management Unit (S12CPMU)
10.4.6
10.4.6.1
This mode is the default mode after System Reset or Power-On Reset.
The Bus clock is based on the PLLCLK, the reference clock for the PLL is internally generated (IRC1M).
The PLL is configured to 50 MHz VCOCLK with POSTDIV set to 0x03. If locked (LOCK=1) this results
in a PLLCLK of 12.5 MHz and a Bus clock of 6.25 MHz. The PLL can be re-configured to other bus
frequencies.
The clock sources for COP and RTI can be based on the internal reference clock generator (IRC1M) or the
RC-Oscillator (ACLK).
10.4.6.2
In this mode, the Bus clock is based on the PLLCLK as well (like PEI). The reference clock for the PLL
is based on the external oscillator.
The clock sources for COP and RTI can be based on the internal reference clock generator or on the
external oscillator clock or the RC-Oscillator (ACLK).
This mode can be entered from default mode PEI by performing the following steps:
Loosing PLL lock status (LOCK=0) means loosing the oscillator status information as well (UPOSC=0).
The impact of loosing the oscillator status (UPOSC=0) in PEE mode is as follows:
Application software needs to be prepared to deal with the impact of loosing the oscillator status at any
time.
10.4.6.3
In this mode, the Bus Clock is based on the external oscillator clock. The reference clock for the PLL is
based on the external oscillator.
The clock sources for COP and RTI can be based on the internal reference clock generator or on the
external oscillator clock or the RC-Oscillator (ACLK).
410
1. Configure the PLL for desired bus frequency.
2. Enable the external oscillator (OSCE bit).
3. Wait for oscillator to start-up and the PLL being locked (LOCK = 1) and (UPOSC =1).
4. Clear all flags in the CPMUFLG register to be able to detect any future status bit change.
5. Optionally status interrupts can be enabled (CPMUINT register).
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•
The PLLCLK is derived from the VCO clock (with its actual frequency) divided by four until the
PLL locks again.
The OSCCLK provided to the MSCAN module is off.
System Clock Configurations
PLL Engaged Internal Mode (PEI)
PLL Engaged External Mode (PEE)
PLL Bypassed External Mode (PBE)
MC9S12G Family Reference Manual,
Rev.1.23
Freescale Semiconductor