S9S12G48F0MLH Freescale Semiconductor, S9S12G48F0MLH Datasheet - Page 439

• Manufacturer Part Number: S9S12G48F0MLH
• Description: 16-bit Microcontrollers - MCU 16Bit 48KFlash 4096RAM MSCAN
• Manufacturer: Freescale Semiconductor

Specifications of S9S12G48F0MLH

• Rohs: yes
• Core: S12
• Processor Series: MC9S12G
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 48 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-64
• Mounting Style: SMD/SMT

or level sensitive with polarity control.
of control bits and their effect on the external trigger function
In order to avoid maybe false trigger events please enable the external digital input via ATDDIEN register
first and in the following enable the external trigger mode by bit ETRIGE..
In either level or edge sensitive mode, the first conversion begins when the trigger is received.
Once ETRIGE is enabled a conversion must be triggered externally after writing the ATDCTL5 register.
During a conversion in edge sensitive mode, if additional trigger events are detected the overrun error flag
ETORF is set.
If level sensitive mode is active and the external trigger de-asserts and later asserts again during a
conversion sequence, this does not constitute an overrun. Therefore, the flag is not set. If the trigger is left
active in level sensitive mode when a sequence is about to complete, another sequence will be triggered
immediately.
11.4.2.2
Each ATD input pin can be switched between analog or digital input functionality. An analog multiplexer
makes each ATD input pin selected as analog input available to the A/D converter.
The pad of the ATD input pin is always connected to the analog input channel of the analog mulitplexer.
Each pad input signal is buffered to the digital port register.
Freescale Semiconductor
General-Purpose Digital Port Operation
ETRIGLE
X
X
0
0
1
1
ETRIGP
X
X
0
1
0
1
Table 11-23. External Trigger Control Bits
MC9S12G Family Reference Manual, Rev.1.23
ETRIGE
Table 11-23
0
0
1
1
1
1
SCAN
X
X
X
X
0
1
gives a brief description of the different combinations
Ignores external trigger. Performs one
conversion sequence and stops.
Ignores external trigger. Performs
continuous conversion sequences.
Trigger falling edge sensitive. Performs
one conversion sequence per trigger.
Trigger rising edge sensitive. Performs one
conversion sequence per trigger.
Trigger low level sensitive. Performs
continuous conversions while trigger level
is active.
Trigger high level sensitive. Performs
continuous conversions while trigger level
is active.
Description
Analog-to-Digital Converter (ADC10B8CV2)
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