S9S12G48F0MLH Freescale Semiconductor, S9S12G48F0MLH Datasheet - Page 371

• Manufacturer Part Number: S9S12G48F0MLH
• Description: 16-bit Microcontrollers - MCU 16Bit 48KFlash 4096RAM MSCAN
• Manufacturer: Freescale Semiconductor

Specifications of S9S12G48F0MLH

• Rohs: yes
• Core: S12
• Processor Series: MC9S12G
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 48 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-64
• Mounting Style: SMD/SMT

10.3.2
This section describes all the S12CPMU registers and their individual bits.
Address order is as listed in
10.3.2.1
The CPMUSYNR register controls the multiplication factor of the PLL and selects the VCO frequency
range.
Read: Anytime
Write: Anytime if PROT=0 (CPMUPROT register) and PLLSEL=1 (CPMUCLKS register). Else write has
no effect.
The VCOFRQ[1:0] bits are used to configure the VCO gain for optimal stability and lock time. For correct
PLL operation the VCOFRQ[1:0] bits have to be selected according to the actual target VCOCLK
frequency as shown in
PLL (no locking and/or insufficient stability).
Freescale Semiconductor
0x0034
Reset
W
If PLL has locked (LOCK=1)
R
Register Descriptions
S12CPMU Synthesizer Register (CPMUSYNR)
0
7
VCOFRQ[1:0]
f
frequency f
VCO
Writing to this register clears the LOCK and UPOSC status bits.
must be within the specified VCO frequency lock range. Bus
Table
Figure 10-4. S12CPMU Synthesizer Register (CPMUSYNR)
1
6
bus
Figure
10-1. Setting the VCOFRQ[1:0] bits incorrectly can result in a non functional
must not exceed the specified maximum.
Table 10-1. VCO Clock Frequency Selection
VCOCLK Frequency Ranges
MC9S12G Family Reference Manual, Rev.1.23
32MHz <= f
48MHz < f
10-3.
0
5
Reserved
Reserved
f VCO
VCO
VCO
<= 50MHz
<= 48MHz
=
NOTE
NOTE
1
4
2 f REF
×
S12 Clock, Reset and Power Management Unit (S12CPMU)
×
(
SYNDIV
1
3
VCOFRQ[1:0]
SYNDIV[5:0]
00
01
10
11
+
1
)
0
2
0
1
0
0
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