S9S12G48F0MLH Freescale Semiconductor, S9S12G48F0MLH Datasheet - Page 365

• Manufacturer Part Number: S9S12G48F0MLH
• Description: 16-bit Microcontrollers - MCU 16Bit 48KFlash 4096RAM MSCAN
• Manufacturer: Freescale Semiconductor

Specifications of S9S12G48F0MLH

• Rohs: yes
• Core: S12
• Processor Series: MC9S12G
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 48 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-64
• Mounting Style: SMD/SMT

10.1.3
Freescale Semiconductor
EXTAL
XTAL
VDDR
VDDX
VDDA
VSS
VSSX
VSSA
RESET
4MHz-16MHz
UPOSC
Controlled
Oscillator
(XOSCLCP)
PSTP
Clock
Monitor
External
Pierce
Loop
S12CPMU Block Diagram
ACLK
IRCCLK
OSCCLK
Voltage
Regulator
3.13 to 5.5V
OSCE
COPOSCSEL0
UPOSC=0 clears
MMC
REFDIV[3:0]
COPOSCSEL1
Reference
Lock
detect
VDD, VDDF
LOCK
Divider
(core supplies)
OSCCLK_LCP
Low Voltage Detect VDDA
Power-On Detect
Low Voltage Detect VDDX
COPCLK
Illegal Address Access
REFCLK
FBCLK
MC9S12G Family Reference Manual, Rev.1.23
Figure 10-1. Block diagram of S12CPMU
IRCTRIM[9:0]
Reference
Internal
(IRC1M)
PCE
Clock
COP
Watchdog
Divide by
2*(SYNDIV+1)
SYNDIV[5:0]
VCOFRQ[1:0]
REFFRQ[1:0]
Phase
locked
Loop with
internal
Filter (PLL)
CPMUCOP
monitor fail
Generator
COP time out
to Reset
UPOSC
PORF
LVRF
ILAF
VCOCLK
POSTDIV[4:0]
UPOSC=0 sets PLLSEL bit
Post
Divider
1,2,.,32
divide
by 4
OSCCLK
IRCCLK
RC
Osc.
Generator
S12 Clock, Reset and Power Management Unit (S12CPMU)
Bus Clock
Reset
RTIOSCSEL
OSCCLK
ACLK
COP time out
APICLK
LVDS
RTICLK
PLLCLK
LOCKIE
Autonomous
Periodic
Interrupt (API)
PRE
Real Time
Interrupt (RTI)
LVIE
PLLSEL
divide
by 8
APIE
Oscillator status Interrupt
S12CPMU
RTIE
Power-On Reset
&
CPMURTI
Low Voltage Interrupt
PLL Lock Interrupt
OSCIE
divide
by 2
System Reset
CAN_OSCCLK
(to MSCAN)
BDM Clock
API Interrupt
RTI Interrupt
(Core Clock)
API_EXTCLK
ECLK2X
(Bus Clock)
(to LCD)
IRCCLK
ECLK
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