S9S12G192F0VLL Freescale Semiconductor, S9S12G192F0VLL Datasheet - Page 166

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S9S12G192F0VLL

Manufacturer Part Number
S9S12G192F0VLL
Description
16-bit Microcontrollers - MCU 32Bit 192 Flash 11264RAM
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of S9S12G192F0VLL

Rohs
yes
Core
S12
Processor Series
MC9S12G
Data Bus Width
16 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
192 KB
Data Ram Size
4 KB
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-100
Mounting Style
SMD/SMT

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Quantity
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Part Number:
S9S12G192F0VLL
Manufacturer:
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S9S12G192F0VLL
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Port
AD
Port Integration Module (S12GPIMV1)
168
PAD15
PAD14
PAD13
PAD12
PAD11
PAD10
PAD9
PAD8
Pin
[PT0AD7]/
[PT0AD6]/
[PT0AD5]/
[PT0AD4]/
[PT0AD3]/
[PT0AD2]/
[PT0AD1]/
[PT0AD0]/
KWAD15
KWAD14
KWAD13
KWAD12
KWAD11
KWAD10
ACMPM
AMPM0
ACMPO
ACMPP
KWAD9
KWAD8
DACU0
AMPP0
DACU0
DACU1
Signal
AMP0
AMP1
AN15
AN14
AN13
AN12
AN11
AN10
AN9
AN8
❏ ❏
■ ■ ■ ■ ■ ■ ■ ■
❏ ❏
■ ■ ■ ■ ■ ■ ■ ■
❏ ❏
■ ■ ■ ■ ■ ■ ■ ■
■ ■
■ ■ ■ ■ ■ ■ ■ ■
❏ ❏ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■
■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■
❏ ❏ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■
■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■
■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■
■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■
■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■
■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■
100
MC9S12G Family Reference Manual,
■ ■
■ ■
■ ■
■ ■
Table 2-4. Signals and Priorities
(signal priority on pin from top to bottom)
Signals per Device and Package
64
■ ■
■ ■
■ ■
48
■ ■ ■ ■
■ ■ ■ ■
■ ■ ■ ■
Rev.1.23
32
20
I/O
I/O GPIO with interrupt
I/O GPIO with interrupt
I/O GPIO with interrupt
I/O GPIO with interrupt
I/O GPIO with interrupt
I/O GPIO with interrupt
I/O GPIO with interrupt
I/O GPIO with interrupt
❍ Routing option on pin
O
O
O
O
O
O
Freescale Semiconductor
I
I
I
I
I
I
I
I
I
I
I
I
Signal available on pin
Routing reset location
Not available on pin
DAC0 output unbuffered
ADC analog
DAC0 non-inv. input (+)
ADC analog
DAC0 inverting input (-)
ADC analog
ADC analog
DAC0 output buffered
DAC0 output unbuffered
ACMP inverting input (-)
ADC analog
DAC1 output buffered
DAC1 output unbuffered
ACMP non-inv. input (+)
ADC analog
ACMP unsync. dig. out
ADC analog
ADC analog
Legend
Description

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