S9S12G192F0VLL Freescale Semiconductor, S9S12G192F0VLL Datasheet - Page 756

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S9S12G192F0VLL

Manufacturer Part Number
S9S12G192F0VLL
Description
16-bit Microcontrollers - MCU 32Bit 192 Flash 11264RAM
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of S9S12G192F0VLL

Rohs
yes
Core
S12
Processor Series
MC9S12G
Data Bus Width
16 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
192 KB
Data Ram Size
4 KB
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-100
Mounting Style
SMD/SMT

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Timer Module (TIM16B8CV3)
23.3.2.2
Read: Anytime but will always return 0x0000 (1 state is transient)
Write: Anytime
Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero.
23.3.2.3
Read: Anytime
Write: Anytime
758
Module Base + 0x0001
Module Base + 0x0002
FOC[7:0]
Reset
Reset
Field
7:0
W
W
R
R
OC7M7
FOC7
Note: Force Output Compare Action for Channel 7:0 — A write to this register with the corresponding data
Timer Compare Force Register (CFORC)
Output Compare 7 Mask Register (OC7M)
0
0
0
7
7
bit(s) set causes the action which is programmed for output compare “x” to occur immediately. The action
taken is the same as if a successful comparison had just taken place with the TCx register except the
interrupt flag does not get set. A channel 7 event, which can be a counter overflow when TTOV[7] is set or
a successful output compare on channel 7, overrides any channel 6:0 compares. If forced output compare
on any channel occurs at the same time as the successful output compare then forced output compare
action will take precedence and interrupt flag won’t get set.
OC7M6
FOC6
0
0
0
Figure 23-8. Output Compare 7 Mask Register (OC7M)
6
6
Figure 23-7. Timer Compare Force Register (CFORC)
MC9S12G Family Reference Manual,
Table 23-3. CFORC Field Descriptions
OC7M5
FOC5
0
0
0
5
5
OC7M4
FOC4
0
0
0
4
4
Description
OC7M3
FOC3
0
0
0
3
3
Rev.1.23
OC7M2
FOC2
0
0
0
2
2
OC7M1
Freescale Semiconductor
FOC1
0
0
0
1
1
OC7M0
FOC0
0
0
0
0
0

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