S9S12G192F0VLL Freescale Semiconductor, S9S12G192F0VLL Datasheet - Page 322

• Manufacturer Part Number: S9S12G192F0VLL
• Description: 16-bit Microcontrollers - MCU 32Bit 192 Flash 11264RAM
• Manufacturer: Freescale Semiconductor

Specifications of S9S12G192F0VLL

• Rohs: yes
• Core: S12
• Processor Series: MC9S12G
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 192 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-100
• Mounting Style: SMD/SMT

S12S Debug Module (S12SDBGV2)
The priorities described in
final state has priority followed by the match on the lower channel number (0,1,2). Thus with
SC[3:0]=1101 a simultaneous match0/match1 transitions to final state.
8.3.2.7.2
Read: If COMRV[1:0] = 01
Write: If COMRV[1:0] = 01 and DBG is not armed.
This register is visible at 0x0027 only with COMRV[1:0] = 01. The state control register 2 selects the
targeted next state whilst in State2. The matches refer to the match channels of the comparator match
control logic as depicted in
Register
DBGXCTL control register.
324
Address: 0x0027
SC[3:0]
SC[3:0]
1010
1011
1100
1101
1110
1111
SC[3:0]
0000
0001
0010
0011
0100
Reset
Field
3–0
W
R
(DBGXCTL). Comparators must be enabled by setting the comparator enable bit in the associated
These bits select the targeted next state whilst in State2, based upon the match event.
0
0
7
Debug State Control Register 2 (DBGSCR2)
Figure 8-10. Debug State Control Register 2 (DBGSCR2)
= Unimplemented or Reserved
0
0
6
Table 8-36
Table 8-18. State2 —Sequencer Next State Selection
Figure 8-1
Table 8-16. State1 Sequencer Next State Selection
Either Match0 or Match2 to Final State........Match1 to State2
MC9S12G Family Reference Manual, Rev.1.23
Table 8-17. DBGSCR2 Field Descriptions
Description (Unspecified matches have no effect)
Description (Unspecified matches have no effect)
dictate that in the case of simultaneous matches, a match leading to
0
0
5
and described in
Match1 to State3....... Match0 Final State
Match0 to State1....... Match2 to State3.
Match1 to State1....... Match2 to State3.
0
0
4
Match1 to State3
Match2 to State3
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Section 8.3.2.8.1, “Debug Comparator Control
SC3
0
3
SC2
0
2
Freescale Semiconductor
SC1
0
1
SC0
0
0