S9S12G192F0VLLR Freescale Semiconductor, S9S12G192F0VLLR Datasheet - Page 441

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S9S12G192F0VLLR

Manufacturer Part Number
S9S12G192F0VLLR
Description
16-bit Microcontrollers - MCU 32Bit 192 Flash 11264RAM
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of S9S12G192F0VLLR

Rohs
yes
Core
S12
Processor Series
MC9S12G
Data Bus Width
16 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
192 KB
Data Ram Size
4 KB
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-100
Mounting Style
SMD/SMT

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
S9S12G192F0VLLR
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Chapter 12
Analog-to-Digital Converter (ADC12B8CV2)
Revision History
12.1
The ADC12B8C is a 8-channel, 12-bit, multiplexed input successive approximation analog-to-digital
converter. Refer to device electrical specifications for ATD accuracy.
Freescale Semiconductor
Number
Version
V02.00
V02.01
V02.02
V02.03
V02.04
V02.05
V02.06
V02.07
V02.08
V02.09
V02.10
Introduction
13 May 2009
22. Jun 2012
29. Jun 2012
17 Dec 2009
09 Feb 2010
26 Feb 2010
25 Aug 2010
09 Sep 2010
11 Feb 2011
14 Apr 2010
02 Oct 2012
Revision
Date
13 May 2009
22. Jun 2012
17 Dec 2009
09 Feb 2010
26 Feb 2010
25 Aug 2010
09 Sep 2010
11 Feb 2011
14 Apr 2010
29 Jun 2012
02 Oct 2012
Effective
Date
MC9S12G Family Reference Manual, Rev.1.23
Author
Initial version copied from V01.05,
changed unused Bits in ATDDIEN to read logic 1
Updated
description of internal channels.
Updated register ATDDR (left/right justified result) description
in section
added
Fixed typo in
resolution
Corrected
description of internal channels.
Corrected typos to be in-line with SoC level pin naming
conventions for VDDA, VSSA, VRL and VRH.
Removed feature of conversion during STOP and general
wording clean up done in
Description
Update of internal only information.
Connectivity Information regarding internal channel_6 added
to
Updated register wirte access information in section
12.3.2.9/12-461
Removed IP name in block diagram
Added user information to avoid maybe false external trigger
events when enabling the external trigger mode
(Section 12.4.2.1, “External Trigger
Table
Table 12-21
12-15.
Table 12-15
12.3.2.12.1/12-463
Table 12-15
Table 12-9
Description of Changes
to improve feature description.
Analog Input Channel Select Coding -
Analog Input Channel Select Coding -
- conversion result for 3mV and 10bit
Section 12.4, “Functional
and
12.3.2.12.2/12-464
Input).
Figure 12-1
and
443

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