S9S12G192F0VLLR Freescale Semiconductor, S9S12G192F0VLLR Datasheet - Page 628

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S9S12G192F0VLLR

Manufacturer Part Number
S9S12G192F0VLLR
Description
16-bit Microcontrollers - MCU 32Bit 192 Flash 11264RAM
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of S9S12G192F0VLLR

Rohs
yes
Core
S12
Processor Series
MC9S12G
Data Bus Width
16 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
192 KB
Data Ram Size
4 KB
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-100
Mounting Style
SMD/SMT

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
S9S12G192F0VLLR
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Freescale’s Scalable Controller Area Network (S12MSCANV3)
Due to independent clock domains within the MSCAN, INITRQ must be synchronized to all domains by
using a special handshake mechanism. This handshake causes additional synchronization delay (see
Figure
If there is no message transfer ongoing on the CAN bus, the minimum delay will be two additional bus
clocks and three additional CAN clocks. When all parts of the MSCAN are in initialization mode, the
INITAK flag is set. The application software must use INITAK as a handshake indication for the request
(INITRQ) to go into initialization mode.
18.4.5
If the MSCAN is disabled (CANE = 0), the MSCAN clocks are stopped for power saving.
If the MSCAN is enabled (CANE = 1), the MSCAN has two additional modes with reduced power
consumption, compared to normal mode: sleep and power down mode. In sleep mode, power consumption
is reduced by stopping all clocks except those to access the registers from the CPU side. In power down
mode, all clocks are stopped and no power is consumed.
Table 18-38
modes is entered by the given settings on the CSWAI and SLPRQ/SLPAK bits.
630
18-45).
Low-Power Options
summarizes the combinations of MSCAN and CPU modes. A particular combination of
The CPU cannot clear INITRQ before initialization mode (INITRQ = 1 and
INITAK = 1) is active.
Bus Clock Domain
CPU
Init Request
INITAK
Flag
Figure 18-45. Initialization Request/Acknowledge Cycle
MC9S12G Family Reference Manual,
INITRQ
sync.
INITAK
NOTE
SYNC
SYNC
CAN Clock Domain
Rev.1.23
sync.
INITRQ
INITAK
INIT
Flag
Freescale Semiconductor

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