S9S12G192F0VLLR Freescale Semiconductor, S9S12G192F0VLLR Datasheet - Page 759

• Manufacturer Part Number: S9S12G192F0VLLR
• Description: 16-bit Microcontrollers - MCU 32Bit 192 Flash 11264RAM
• Manufacturer: Freescale Semiconductor

Specifications of S9S12G192F0VLLR

• Rohs: yes
• Core: S12
• Processor Series: MC9S12G
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 192 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-100
• Mounting Style: SMD/SMT

23.3.2.7
Read: Anytime
Write: Anytime
Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero.
Freescale Semiconductor
Module Base + 0x0007
TOV[7:0]
TSFRZ
TFFCA
Reset
PRNT
Field
Field
7:0
5
4
3
W
R
TOV7
Timer Stops While in Freeze Mode
0 Allows the timer counter to continue running while in freeze mode.
1 Disables the timer counter whenever the MCU is in freeze mode. This is useful for emulation.
TSFRZ does not stop the pulse accumulator.
Timer Fast Flag Clear All
0 Allows the timer flag clearing to function normally.
1 For TFLG1(0x000E), a read from an input capture or a write to the output compare channel (0x0010–0x001F)
Precision Timer
0 Enables legacy timer. PR0, PR1, and PR2 bits of the TSCR2 register are used for timer counter prescaler
1 Enables precision timer. All bits of the PTPSR register are used for Precision Timer Prescaler Selection, and
This bit is writable only once out of reset.
Toggle On Overflow Bits — TOVx toggles output compare pin on overflow. This feature only takes effect when
in output compare mode. When set, it takes precedence over forced output compare but not channel 7 override
events.
0 Toggle output compare pin on overflow feature disabled.
1 Toggle output compare pin on overflow feature enabled.
Timer Toggle On Overflow Register 1 (TTOV)
0
7
causes the corresponding channel flag, CnF, to be cleared. For TFLG2 (0x000F), any access to the TCNT
register (0x0004, 0x0005) clears the TOF flag. Any access to the PACNT registers (0x0022, 0x0023) clears
the PAOVF and PAIF flags in the PAFLG register (0x0021) if channel 7 exists. This has the advantage of
eliminating software overhead in a separate clear sequence. Extra care is required to avoid accidental flag
clearing due to unintended accesses.
selection.
all bits.
Figure 23-13. Timer Toggle On Overflow Register 1 (TTOV)
TOV6
0
6
Table 23-6. TSCR1 Field Descriptions (continued)
MC9S12G Family Reference Manual, Rev.1.23
Table 23-7. TTOV Field Descriptions
TOV5
0
5
TOV4
0
4
Description
Description
TOV3
0
3
TOV2
0
2
Timer Module (TIM16B8CV3)
TOV1
0
1
TOV0
0
0
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