S9S12G192F0VLLR Freescale Semiconductor, S9S12G192F0VLLR Datasheet - Page 592

• Manufacturer Part Number: S9S12G192F0VLLR
• Description: 16-bit Microcontrollers - MCU 32Bit 192 Flash 11264RAM
• Manufacturer: Freescale Semiconductor

Specifications of S9S12G192F0VLLR

• Rohs: yes
• Core: S12
• Processor Series: MC9S12G
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 192 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-100
• Mounting Style: SMD/SMT

Freescale’s Scalable Controller Area Network (S12MSCANV3)
18.3.2.3
The CANBTR0 register configures various CAN bus timing parameters of the MSCAN module.
1
594
Module Base + 0x0002
Read: Anytime
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
SJW[1:0]
BRP[5:0]
SLPAK
INITAK
Field
Field
7-6
5-0
1
0
Reset:
W
R
Sleep Mode Acknowledge — This flag indicates whether the MSCAN module has entered sleep mode (see
Section 18.4.5.5, “MSCAN Sleep
Sleep mode is active when SLPRQ = 1 and SLPAK = 1. Depending on the setting of WUPE, the MSCAN will
clear the flag if it detects activity on the CAN bus while in sleep mode.
0 Running — The MSCAN operates normally
1 Sleep mode active — The MSCAN has entered sleep mode
Initialization Mode Acknowledge — This flag indicates whether the MSCAN module is in initialization mode
(see
mode request. Initialization mode is active when INITRQ = 1 and INITAK = 1. The registers CANCTL1,
CANBTR0, CANBTR1, CANIDAC, CANIDAR0–CANIDAR7, and CANIDMR0–CANIDMR7 can be written only by
the CPU when the MSCAN is in initialization mode.
0 Running — The MSCAN operates normally
1 Initialization mode active — The MSCAN has entered initialization mode
Synchronization Jump Width — The synchronization jump width defines the maximum number of time quanta
(Tq) clock cycles a bit can be shortened or lengthened to achieve resynchronization to data transitions on the
CAN bus (see
Baud Rate Prescaler — These bits determine the time quanta (Tq) clock which is used to build up the bit timing
(see
MSCAN Bus Timing Register 0 (CANBTR0)
SJW1
Section 18.4.4.5, “MSCAN Initialization
Table
0
7
18-7).
Table 18-4. CANCTL1 Register Field Descriptions (continued)
Table
Figure 18-6. MSCAN Bus Timing Register 0 (CANBTR0)
SJW1
SJW0
Table 18-5. CANBTR0 Register Field Descriptions
0
0
1
1
6
0
18-6).
Table 18-6. Synchronization Jump Width
MC9S12G Family Reference Manual,
BRP5
0
Mode”). It is used as a handshake flag for the SLPRQ sleep mode request.
5
Mode”). It is used as a handshake flag for the INITRQ initialization
BRP4
SJW0
4
0
0
1
0
1
Description
Description
BRP3
0
3
Rev.1.23
Synchronization Jump Width
BRP2
2 Tq clock cycles
3 Tq clock cycles
4 Tq clock cycles
2
0
1 Tq clock cycle
Access: User read/write
Freescale Semiconductor
BRP1
0
1
BRP0
0
0
1