5SGXMA4H2F35I3LN Altera Corporation, 5SGXMA4H2F35I3LN Datasheet - Page 10

• Manufacturer Part Number: 5SGXMA4H2F35I3LN
• Description: FPGA - Field Programmable Gate Array FPGA - Stratix V GX 1900 LABS 552 IOs
• Manufacturer: Altera Corporation
• Series: Stratix V GXr

Specifications of 5SGXMA4H2F35I3LN

• Rohs: yes
• Number Of Logic Blocks: 1900
• Number Of I/os: 552
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-1152
• Distributed Ram: 37 Mbit
• Minimum Operating Temperature: - 40 C

Page 10
Low-Power Serial Transceivers
Figure 1. Stratix V GT, GX, and GS Device Chip View
Stratix V Device Overview
Notes to
(1) This figure represents a given variant of a Stratix V device with transceivers. Other variants may have a different floorplan than the one shown
(2) You can use the unused transceiver channels as additional transceiver transmitter PLLs.
here.
Figure
1:
Stratix V FPGAs deliver the industry’s most flexible transceivers with the highest
bandwidth from 600 Mbps to 28.05 Gbps, low bit error ratio (BER), and low power.
Stratix V transceivers have many enhancements to improve flexibility and robustness.
These enhancements include robust analog receiver clock and data recovery (CDR),
advanced pre-emphasis, and equalization. In addition, all transceivers are identical
with the full featured embedded PCS hard IP to simplify the design, lower the power,
and save valuable core resources.
Stratix V transceivers are compliant with a wide range of standard protocols and data
rates and are equipped with a variety of signal-conditioning features to support
backplane, optical module, and chip-to-chip applications.
Stratix V transceivers are located on the left and right sides of the device, as shown in
Figure
I/O noise from coupling into the transceivers, thereby ensuring optimal signal
integrity. The transceiver channels consist of the physical medium attachment (PMA),
PCS, and high-speed clock networks. You can also use the unused transceiver PMA
channels as additional transmitter PLLs.
1. The transceivers are isolated from the rest of the chip to prevent core and
I/O, LVDS, and Memory Interface
I/O, LVDS, and Memory Interface
Core Logic
Fabric
Core Logic
Fabric
(1)
Table 6
lists the transceiver PMA features.
PCS
PCS
PCS
PCS
PCS
December 2012 Altera Corporation
Low-Power Serial Transceivers
PMA
PMA
PMA
PMA
PMA
(2)