5SGXMA4H2F35I3LN Altera Corporation, 5SGXMA4H2F35I3LN Datasheet - Page 11

• Manufacturer Part Number: 5SGXMA4H2F35I3LN
• Description: FPGA - Field Programmable Gate Array FPGA - Stratix V GX 1900 LABS 552 IOs
• Manufacturer: Altera Corporation
• Series: Stratix V GXr

Specifications of 5SGXMA4H2F35I3LN

• Rohs: yes
• Number Of Logic Blocks: 1900
• Number Of I/os: 552
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-1152
• Distributed Ram: 37 Mbit
• Minimum Operating Temperature: - 40 C

Low-Power Serial Transceivers
Table 6. Transceiver PMA Features
Table 7. Transceiver PCS Features (Part 1 of 2)
December 2012 Altera Corporation
Backplane support
Cable driving support
Optical module support with EDC
Chip-to-chip support
Continuous Time Linear Equalization
(CTLE)
Decision Feedback Equalization (DFE)
Adaptive equalization (AEQ)
PLL-based clock recovery
Programmable deserialization and word
alignment
Transmitter equalization (pre-emphasis)
Ring and LC oscillator transmitter PLLs
On-chip instrumentation (EyeQ data-eye
monitor)
Dynamic reconfiguration
Protocol support
Custom PHY
Custom 10G PHY
x1, x4, x8 PCIe
Gen1 and Gen2
Protocol
Feature
Data Rates (Gbps)
Table 6
The Stratix V core logic connects to the PCS through an 8-, 10-, 16-, 20-, 32-, 40-, 64-, or
66-bit interface, depending on the transceiver data rate and protocol. Stratix V devices
contain PCS hard IP to support PCIe Gen3, Gen2, Gen1, Interlaken, 10GE, XAUI, GbE,
SRIO, CPRI, and GPON protocols. All other standard and proprietary protocols are
supported through the transceiver PCS hard IP.
features.
9.98 to 14.1
2.5 and 5.0
0.6 to 8.5
lists the PMA features for the Stratix V transceivers.
Receiver 5-tap digital equalizer to minimize losses and crosstalk
14.1 Gbps (Stratix V GX and GS devices), 12.5 Gbps (Stratix V GT devices)
PCIe cable and eSATA applications
10G Form-factor Pluggable (XFP), Small Form-factor Pluggable (SFP+), Quad
Small Form-factor Pluggable (QSFP), CXP, 100G Pluggable (CFP), 100G Form-
factor Pluggable
28.05 Gbps and 12.5 Gbps (Stratix V GT devices) and 14.1 Gbps (Stratix V GX
and GS devices)
Receiver 4-stage linear equalization to support high-attenuation channels
Adaptive engine to automatically adjust equalization to compensate for changes
over time
Superior jitter tolerance versus phase interpolation techniques
Flexible deserialization width and configurable word alignment patterns
Transmitter driver 4-tap pre-emphasis and de-emphasis for protocol
compliance under lossy conditions
Choice of transmitter PLLs per channel, optimized for specific protocols and
applications
Allows non-intrusive on-chip monitoring of both width and height of the data
eye
Allows reconfiguration of single channels without affecting operation of other
channels
Compliance with over 50 industry standard protocols in the range of 600 Mbps
to 28.05 Gbps
Phase compensation FIFO, byte
serializer, 8B/10B encoder, bit-slip,
and channel bonding
TX FIFO, gear box, and bit-slip
Same as custom PHY plus PIPE 2.0
interface to core logic
Transmitter Data Path
Capability
Table 7
Word aligner, de-skew FIFO, rate
match FIFO, 8B/10B decoder, byte
deserializer, and byte ordering
RX FIFO and gear box
Same as custom PHY plus PIPE 2.0
interface to core logic
lists the transceiver PCS
Receiver Data Path
Stratix V Device Overview
Page 11