MCIMX508CZK8B Freescale Semiconductor, MCIMX508CZK8B Datasheet
MCIMX508CZK8B
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MCIMX508CZK8B Summary of contents
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... WLAN, Bluetooth™, GPS, and displays. © 2013 Freescale Semiconductor, Inc. All rights reserved. Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. ...
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... Pixel Processing Pipeline (ePXP) The ePXP is a high-performance pixel processor capable of 1 pixel/clock performance for combined operations, such as color-space conversion, alpha blending, gamma mapping, and i.MX50 Applications Processors for Consumer Products, Rev EPD panels, supporting a wide variety of Section 1.1.4, “Graphics Accelerators”). Freescale Semiconductor ...
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... Unified L2 cache • 800 MHz target frequency of the core (including NEON, VFPv3, and L1 cache) • NEON coprocessor (SIMD Media Processing Architecture) and Vector Floating Point (VFP-Lite) coprocessor supporting VFPv3 i.MX50 Applications Processors for Consumer Products, Rev. 4 Freescale Semiconductor Introduction ...
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... Pixel processing pipeline (ePXP) – Electrophoretic display controller (EPDC) – eLCDIF LCD display controller – DCP Crypto engine – BCH ECC engine – MAX AHB crossbar – GPU 2D – SDMA i.MX50 Applications Processors for Consumer Products, Rev Freescale Semiconductor ...
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... On the i.MX508, both displays can be active simultaneously. If both displays are active, the eLCDIF only provides a 16-bit interface due to pin muxing. • Expansion cards: — Four SD/MMC card • USB: — One High Speed (HS) USB 2.0 OTG-capable port with integrated HS USB PHY i.MX50 Applications Processors for Consumer Products, Rev. 4 Freescale Semiconductor NOTE Introduction 5 ...
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... Secure real-time clock (SRTC)—Tamper resistant RTC with dedicated power domain and mechanism to detect voltage and clock glitches • Advanced high assurance boot (A-HAB)—HAB with the next embedded enhancements: SHA-256, 2048-bit RSA key, version control mechanism, warm boot, CSU, and TZ initialization i.MX50 Applications Processors for Consumer Products, Rev Freescale Semiconductor ...
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... Ordering Information Table 1 provides the ordering information. Part Number Mask Set MCIMX508CVK8B N78A Full Specification MCIMX508CZK8B N78A Full Specification MCIMX508CVM8B N78A Full Specification MCIMX507CVM8B N78A No GPU MCIMX507CVK8B N78A No GPU MCIMX503CVK8B N78A No EPD controller MCIMX503CVM8B N78A No EPD controller MCIMX503EVM8B N78A No EPD controller, ...
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... IOMUX with another ALT-mode setting. Table 3. Package Feature Comparison I/O Pin Differences Notes on Package Differences • USB_OTG_VDDA25 and USB_H1_VDDA25 are shorted together on the 416 MAPBGA package substrate. • USB_OTG_VDDA33 and USB_H1_VDDA33 are shorted together on the 416 MAPBGA package substrate. Comments Freescale Semiconductor ...
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... DRAM_SDCLK_1_B DRAM_A14 DRAM_SDODT1 UART2_CTS UART2_RTS i.MX50 Applications Processors for Consumer Products, Rev. 4 Freescale Semiconductor I/O Pin Differences Notes on Package Differences • The i.MX50 PoPBGA package supports 168-FBGA LPDDR2 DRAM memory only not possible to support LPDDR1 or DDR2 on the i.MX50 PoPBGA. • i.MX50 PoPBGA was designed to accommodate a combined LPDDR2 / eMMC PoP memory ...
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... Architectural Overview 2 Architectural Overview The following sections provide an architectural overview of the i.MX50 processor system. 2.1 Block Diagram Figure 1 shows the functional modules in the i.MX50 processor system. i.MX50 Applications Processors for Consumer Products, Rev Figure 1. i.MX50 System Block Diagram Freescale Semiconductor ...
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... Clock Amplifier Clocks, Resets, and Power Control i.MX50 Applications Processors for Consumer Products, Rev. 4 Freescale Semiconductor NOTE Table 4. i.MX50 Digital and Analog Modules The ARM Cortex-A8 Core Platform consists of the ARM Cortex-A8 processor and its essential sub-blocks. It contains the 32 Kbyte L1 instruction cache, 32 Kbyte L1 data cache, Level 2 cache controller and a 256 Kbyte L2 cache ...
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... Each EPIT is a 32-bit set and forget timer that starts counting after the EPIT is enabled by software capable of providing precise interrupts at regular intervals with minimal processor intervention. It has a 12-bit prescaler for division of input clock frequency to get the required time setting for the interrupts to occur, and counter values can be programmed on the fly. Freescale Semiconductor ...
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... GPT General Timer Purpose Timer Peripherals i.MX50 Applications Processors for Consumer Products, Rev. 4 Freescale Semiconductor Brief Description Ultra High-Speed eSDHC, enhanced to support eMMC 4.4 standard specification, for 832 Mbps backward compatible to eSDHCv2 IP. See complete features listing in eSDHCv2 entry below. Port 3 is specifically enhanced to support eMMC 4.4 specification, for double data rate (832 Mbps, 8-bit port) ...
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... The On-Chip Memory controller (OCRAM) module interface between the system’s AXI bus, to the internal (on-chip) SRAM memory module used for controlling the 128 Kbyte multimedia RAM, through a 64-bit AXI bus. Supports secure and regular Boot Modes. The ROM Controller supports ROM Patching. Freescale Semiconductor ...
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... Secure Real Security Time Clock Peripherals i.MX50 Applications Processors for Consumer Products, Rev. 4 Freescale Semiconductor Brief Description The SDMA is multi-channel flexible DMA engine. It helps in maximizing system performance by offloading various cores in dynamic data routing. The SDMA features list is as follows: • Powered by a 16-bit instruction-set micro-RISC engine • ...
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... The WDOG Timer supports two comparison points during each counting period. Each of the comparison points is configurable to invoke an interrupt to the ARM core, and a second point invokes an external event on the WDOG line. The XTALOSC module combined with an external 24 MHz crystal with load capacitors implements a crystal oscillator. Freescale Semiconductor ...
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... Care must be taken to minimize external leakages on ECKIL and CKIL. If they are significant to the 14 MΩ feedback or 1 μA, then loss of oscillation margin or cessation of oscillation may result. i.MX50 Applications Processors for Consumer Products, Rev. 4 Freescale Semiconductor Section 5, “Package Information and Contact Table 5. Special Signal Considerations Remarks ...
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... NVCC_SRTC power. This may be useful for an alarm application allows the i.MX50 to turn off all blocks except for the RTC and then power on again at a specified time. This output is in the NVCC_SRTC domain. i.MX50 Applications Processors for Consumer Products, Rev Remarks Freescale Semiconductor ...
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... If USB_H1 is not used, the H1 RREFEXT resistor may be eliminated and the pin left floating. If USB_OTG is not used, the OTG RREFEXT resistor may be eliminated and the pin left floating. i.MX50 Applications Processors for Consumer Products, Rev. 4 Freescale Semiconductor Remarks Modules List 19 ...
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... These electrical specifications are preliminary. These specifications are not fully tested or guaranteed at this early stage of the product life cycle. Finalized specifications are published after thorough characterization and device qualifications have been completed. i.MX50 Applications Processors for Consumer Products, Rev Remarks NOTE Freescale Semiconductor ...
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... Memory array supply Supply voltage (HVIO) Supply voltage (GPIO, LVIO) Input/output voltage range USB VBUS Transient (t<30ms, duty cycle < 0.05%) i.MX50 Applications Processors for Consumer Products, Rev. 4 Freescale Semiconductor Table 6. i.MX50 Chip-Level Conditions CAUTION Table 7 may cause permanent damage to Table 7. Absolute Maximum Ratings Symbol ...
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... Four layer board (2s2p) — — 6 — Min Max Unit V — 2000 — 500 o –40 125 C Symbol Value Unit R 51 °C/W θ °C/W θ °C/W θJMA R 24 °C/W θJMA R 14 °C/W θ °C/W θJC Ψ 2 °C/W JT Freescale Semiconductor ...
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... Per JEDEC JESD51-2 with the single layer board horizontal. The thermal test board meets JESD51-9 specification. i.MX50 Applications Processors for Consumer Products, Rev. 4 Freescale Semiconductor Thermal Resistance Data Board 1, 2 Single layer board (1s) ...
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... Applications Processors for Consumer Products, Rev Table 11. i.MX50 Operating Ranges Parameter ≤ 800 MHz ≤ 400 MHz ≤ 167 MHz Minimum Nominal Maximum 0.95 1.05 1.15 0.85 0.95 1.15 0.8 0.9 1.15 0.75 0.85 1.15 0.9 0.95 1.275 3 1 1.05 1.275 1.175 1.225 1.275 1.15 1.20 1.275 3 0.9 0.95 1.275 2.7 3.0 3.3 2.375 2.5 2.625 1.15 1.2 1.32 1.75 1.8 1.95 1.65 1.875 or 3.1 2.775 1.71 1.8 1.95 1.14 1.2 1.3 Freescale Semiconductor Unit ...
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... USB_OTG_VDDA25 and USB_H1_VDDA25 are shorted together on the 416 MAPBGA and 416 PoPBGA package substrates. 5 USB_OTG_VDDA33 and USB_H1_VDDA33 are shorted together on the 416 MAPBGA and 416 PoPBGA package substrates. i.MX50 Applications Processors for Consumer Products, Rev. 4 Freescale Semiconductor Parameter HVIO_L HVIO_H and Table 77 for details ...
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... Applications Processors for Consumer Products, Rev Table 12. Interface Frequency Symbol Min f See Table 63 tck f 32.768 ckil f See Table 37 ckih f 22 xtal Table 13. E-Fuse Supply Current Symbol I program ). program Max Unit MHz 1 kHz MHz 27 MHz Min Typ Max Unit — Freescale Semiconductor mA ...
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... ARM core in STOP mode and power gated • VDDGP, VCC, and VDDA/VDDAL1 voltages at suspend levels • VDD3P0, VDD2P5, VDD1P8, and VDD1P2 powered off • USB_VDDA25 and USB_VDDA33 powered off i.MX50 Applications Processors for Consumer Products, Rev. 4 Freescale Semiconductor Supply VDDGP VCC VDDA/VDDAL1 VDD1P2 VDD1P8 1 ...
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... Applications Processors for Consumer Products, Rev Conditions Typical @ 25 °C Full speed RX TX High speed RX TX Full speed RX TX High speed RX TX Full speed RX TX High speed RX TX Max Unit Freescale Semiconductor ...
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... When the i.MX50 is resuming from STOP mode, there are some special sequencing considerations. The resume timing is determined by the following internal counters: 1. STBY_COUNT. This register is in the CCM block and may be set to a maximum kHz cycles, or 500 μsec. i.MX50 Applications Processors for Consumer Products, Rev. 4 Freescale Semiconductor Figure 2. Power-Up Sequence NOTE Electrical Characteristics 29 ...
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... Low-level output voltage i.MX50 Applications Processors for Consumer Products, Rev NOTE Symbol Test Conditions Voh Ioh=-1mA Ioh=spec’ed Drive Vol Iol=1mA Iol=specified Drive Table 11, unless otherwise noted. MIN Typ MAX OVDD-0.15 — — 0.8*OVDD — — 0.15 0.2*OVDD Freescale Semiconductor Units V V ...
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... Pull-up resistor (100 KΩ PU) Pull-down resistor (100 KΩ PD) Input current (no pull-up/down) Input current (22 KΩ PU) Input current (47 KΩ PU) Input current (100 KΩ PU) i.MX50 Applications Processors for Consumer Products, Rev. 4 Freescale Semiconductor Symbol Test Conditions I Voh=0.8*OVDD Low Drive Ioh ...
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... Vref-0.125 -0.3 — ovdd+0.3 0.25 — ovdd+0.6 Vref Vref+0.04 — 0. 360 — 2.3 480 — 6.4 750 — 3.1 720 Freescale Semiconductor Units μA KΩ Units — — ...
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... DC input differential voltage 3 Input current (no pull-up/down) 3 Tri-state I/O supply current Tri-state 2.5V predrivers supply 3 current 3 Tri-state core supply current i.MX50 Applications Processors for Consumer Products, Rev. 4 Freescale Semiconductor Table 11, unless otherwise noted. Symbol Test Conditions Voh — Vol — Vref — Vih(dc) — ...
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... Freescale Semiconductor Units KΩ KΩ KΩ KΩ nA μA μA μA ...
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... Low-level output current, low voltage mode Low-level output current, high voltage mode 1 High-Level DC input voltage Low-Level DC input voltage Input Hysteresis 2 Schmitt trigger VT+ Schmitt trigger VT- i.MX50 Applications Processors for Consumer Products, Rev. 4 Freescale Semiconductor Symbol Test Conditions IIN VI=OVDD Rext — Symbol Test Conditions Voh Ioh=-1mA Ioh=spec’ ...
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... Rext — MIN TYP MAX Units KΩ 148 KΩ 156 KΩ 256 KΩ — 2.8 470 nA 50 μA — — 153 0.05 μA — — 77 0.05 μA — — 73 0.05 μA — — 0.47 63 — — -5.1 -10.2 mA -15.3 — — 2.5 KΩ Freescale Semiconductor ...
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... Medium drive strength, Ztl = 75 Ω impedance High drive strength, Ztl = 50 Ω Max drive strength, Ztl = 37.5 Ω i.MX50 Applications Processors for Consumer Products, Rev. 4 Freescale Semiconductor Table 23. GPIO Output Buffer Impedance Test Conditions Table 24. LVIO Output Buffer Impedance Test Conditions Electrical Characteristics ...
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... Applications Processors for Consumer Products, Rev Table 25. HVIO Output Buffer Impedance Min OVDD OVDD 1.95 V 3.3 V 113.5 103.8 56.2 51.9 37.8 35.1 78.5 70 39.7 34.5 26.8 23 NOTE Typ Max OVDD OVDD OVDD OVDD 1.875 V 3.30V 1.65 V 2.68 V 130.6 133 219.4 212.2 66 69.2 109.7 111.1 45.9 41 73.1 71.8 113.6 102 230.8 179.5 56.8 50 115.4 89.8 38.3 33.3 76.9 60.7 Figure 3). Freescale Semiconductor Unit Ω Ω ...
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... OVDD Vref1 Vref 0 Vovdd – Vref1 Rpu = Rpd = Vovdd – Vref2 Figure 3. Impedance Matching Load for Measurement i.MX50 Applications Processors for Consumer Products, Rev. 4 Freescale Semiconductor OVDD PMOS (Rpu) Ztl inches Pad NMOS (Rpd) OVSS Vref2 × Ztl Vref1 Vref2 × ...
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... Figure 4 and Figure 5. The AC Table 26 and Table 27, respectively. NVCC 80% 20 Min Typ Max 1.91/1.52 3.07/2.65 2.22/1.81 3.81/3.42 2.88/2.42 5.43/5.02 4.94/4.50 10.55/9.70 0.5/0.65 0.32/0.37 0.43/0.54 0.26/0.41 0.34/0.41 0.18/0.2 0.20/0.22 0.09/0.1 30 Freescale Semiconductor Unit V/ns V/ns V/ns V/ns mA/ns ...
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... VIL to VIH for rising edge and between VIH to VIL for falling edge. 2 Hysteresis mode is recommended for inputs with transition time greater than 25 ns. i.MX50 Applications Processors for Consumer Products, Rev. 4 Freescale Semiconductor Symbol Test Condition tdit tdit tdit trm Table 27 ...
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... Symbol Test Condition tps tps tps tps tdit tdit tdit tdit trm Min Typ Max 1.97/1.57 3.12/2.70 2.29/1.87 3.79/3.44 2.93/2.48 5.42/4.98 4.92/4.57 10.64/9.85 0.50/0.63 0.32/0.37 0.43/0.53 0.26/0.29 0.34/0.40 0.18/0.20 0.20/0.22 0.09/0. Freescale Semiconductor Unit V/ns V/ns V/ns V/ns mA/ns mA/ns mA/ns mA/ns ns ...
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... Table 30. HVIO I/O Low Voltage (1 Parameters Parameter Output Pad Transition Times (High Drive) Output Pad Transition Times (Medium Drive) Output Pad Transition Times (Low Drive) i.MX50 Applications Processors for Consumer Products, Rev. 4 Freescale Semiconductor Table 29. LVIO I/O Fast AC Parameters Symbol Test Condition tr ...
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... Typ Max Unit V/ns V/ns V/ns 34 mA/ns 22 mA/ns 11 mA/ Typ Max Unit 2.16/1.79 ns 3.75/3.28 2.81/2.40 ns 5.06/4.58 4.69/4.15 ns 8.91/8.51 V/ns V/ns V/ns — 55 mA/ns — 36 mA/ns — 16 mA/ns — Freescale Semiconductor ...
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... OVDD. Vix(ac) indicates the voltage at which differential input signal must cross. 3 The typical value of Vox(ac) is expected to be about 0.5*OVDD and Vox(ac) is expected to track variation in OVDD. Vox(ac) indicates the voltage at which differential output signal must cross. i.MX50 Applications Processors for Consumer Products, Rev. 4 Freescale Semiconductor Table 32. DDR2 I/O AC Parameters Symbol Vih(ac) Vref+0.25 ...
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... Vix(ac) 0.4*ovdd t POHLD t POLHD t PIHLD t PILHD tsr 0.3 Table 34. LPDDR2 I/O AC Parameters Symbol Min Vih(ac) Vref+0.22 Vil(ac) ovss 1 Vidh(ac) 0.44 Vidhl(ac) Vix(ac) -0.12 Vpeak Varea t POHLD t POLHD t PIHLD t PILHD Max Unit ovdd+0.3 0.2*ovdd ovdd+0.6 V 0.6*ovdd 2.5 ns 2.5 1.5 1.5 2.5 V/ns Max Unit ovdd Vref-0. 0.44 0.12 0.35 ns 0.6 (at 266 V-ns MHz) 3.5 ns 3.5 1.5 1.5 Freescale Semiconductor ...
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... Duration of RESET_IN_B assertion to be qualified as valid (input slope = 5 ns) 4.6.2 WDOG Reset Timing Parameters Figure 7 shows the WDOG reset timing and WDOG_RST_B (Input) i.MX50 Applications Processors for Consumer Products, Rev. 4 Freescale Semiconductor Symbol tsr tsr Table 35 lists the timing parameters. CC1 Figure 6. Reset Timing Diagram Table 35. Reset Timing Parameters ...
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... Typ Max Unit — 40.0 MHz — 0.3 — 3 — VDD Vp Min Typ Max 10 — 100 10 — 40 300 — 1025 1 — — 15 –67108862 — 67108862 1 — 67108863 48.5 50 51.5 Freescale Semiconductor Unit T CKIL Unit MHz MHz MHz — — — — % ...
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... Asynchronous mode AC timings are provided as multiplications of the clock cycle and fixed delay. The Maximum I/O speed of GPMI in Asynchronous mode is about 50 MB/s. and Figure 11 depict the relative timing between GPMI signals at the module level for different i.MX50 Applications Processors for Consumer Products, Rev. 4 Freescale Semiconductor Test Conditions/Remarks — — — FPL mode, integer and fractional 300 MHz @ avdd = 1 ...
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... Figure 9. Address Latch Cycle Timing Diagram i.MX50 Applications Processors for Consumer Products, Rev Table 39 describes the timing parameters (NF1–NF17) that are NF2 NF1 NF3 NF5 NF6 NF7 NF8 NF9 Command NF1 NF4 NF3 NF10 NF11 NF5 NF7 NF6 NF8 NF9 Address NF4 Freescale Semiconductor ...
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... Table 39. Asynchronous Mode Timing Parameters ID Parameter NF1 CLE setup time NF2 CLE hold time NF3 CEn setup time NF4 CE hold time i.MX50 Applications Processors for Consumer Products, Rev. 4 Freescale Semiconductor NF1 NF3 NF10 NF11 NF5 NF6 NF8 NF9 Data to NF NF14 NF15 ...
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... DS*T — tRC (DS+DH)*T — tREH DH*T tDSR N/A tDHR N/A 1 (continued) Example Timing for ≈ 100 GPMI Clock MHz 10ns Min. Max — 20 — 10 — 10 — — 10 — 20 — 10 — 10 — 10 — Freescale Semiconductor Unit ...
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... CE_N CLE ALE CLK W/R# DQS DQS output enable DQ[7:0] DQ[7:0] Output enable Figure 12. Source Synchronous Mode Command and Address Timing Diagram i.MX50 Applications Processors for Consumer Products, Rev. 4 Freescale Semiconductor NF20 NF21 NF20 CMD ADD NF23 Electrical Characteristics NF19 NF21 NF22 ADD NF24 53 ...
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... Electrical Characteristics NF18 CE_N CLE ALE CLK W/R# DQS DQS output enable DQ[7:0] DQ[7:0] Output enable Figure 13. Source Synchronous Mode Data Write Timing Diagram i.MX50 Applications Processors for Consumer Products, Rev NF25 NF23 NF25 NF22 NF27 NF27 NF19 NF26 NF24 NF27 Freescale Semiconductor ...
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... NF18 CE# access time NF19 CE# hold time NF20 Command/address DQ setup time NF21 Command/address DQ hold time NF22 clock period NF23 preamble delay i.MX50 Applications Processors for Consumer Products, Rev. 4 Freescale Semiconductor NF25 NF22 T = GPMI Clock Cycle Symbol Min. t CE_DELAY 0 0.5*t CAS ...
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... Async mode AC timing. Please refer to the above chapter for details. i.MX50 Applications Processors for Consumer Products, Rev Timing T = GPMI Clock Cycle Symbol Min. t POST_DELAY*t POST CK t 0.5*t CALS CK t 0.5*t CALH DQSS CK NOTE 1 (continued) Unit Max. — ns — ns — ns — ns Freescale Semiconductor ...
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... Read and Write Timing dev_clk CE_N 0 0 CLE ALE 0 WE_N 1 RE_N 1 DQS 0.5 tCK DQ[7:0] Figure 15. Samsung Toggle Mode Data Write Timing i.MX50 Applications Processors for Consumer Products, Rev. 4 Freescale Semiconductor NF22 NF23 Electrical Characteristics NF24 0.5 tCK 57 ...
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... Command/address DQ hold time NF22 clock period i.MX50 Applications Processors for Consumer Products, Rev NF23 1 tCK 1 tCK T = GPMI Clock Cycle Symbol Min. t CE_DELAY 0 0.5*t CAS CK t 0.5*t CAH CK t 7.5 CK NF24 1 tCK 1 Timing Unit Max. — ns — ns — ns — ns — ns Freescale Semiconductor ...
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... EIM_BCLK WE4 EIM_ADDR WE6 EIM_CSx WE8 EIM_RW WE10 EIM_OE WE12 EIM_EBx WE14 EIM_LBA WE16 EIM_DATA i.MX50 Applications Processors for Consumer Products, Rev. 4 Freescale Semiconductor T = GPMI Clock Cycle Symbol Min. t (PRE_DELAY+1)*t PRE t POST_DELAY*t POST t 0.5*t CALS CK t 0.5*t CALH CK specify the timings related to the EIM module ...
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... Electrical Characteristics EIM_BCLK EIM_DATA EIM_WAIT i.MX50 Applications Processors for Consumer Products, Rev WE18 WE19 WE20 WE21 Figure 18. EIM Inputs Timing Diagram Freescale Semiconductor ...
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... EIM_BCLK of 66.5 MHz. When the clock branch to EIM is decreased to 66.5 MHz, other buses are impacted which are clocked from this source. See the CCM chapter of the MCIMX50 Applications Processor Reference Manual (MCIMX50RM) for a detailed clock tree description. i.MX50 Applications Processors for Consumer Products, Rev. 4 Freescale Semiconductor Table 42. EIM Bus Timing Parameters BCD = 0 BCD = 1 ...
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... EIM_DATA Figure 19. Synchronous Memory Read Access, WSC=1 i.MX50 Applications Processors for Consumer Products, Rev Figure 22, Figure 23, and Figure 24 WE4 Address v1 WE6 WE14 WE10 WE12 WE18 give a few examples of basic EIM WE5 Next Address WE7 WE15 WE11 WE13 D(v1) WE19 Freescale Semiconductor ...
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... EIM_RW WE14 EIM_LBA WE10 EIM_OE WE12 EIM_EBx EIM_WAIT EIM_DATA Figure 21. Synchronous 16-Bit Memory, Two Non-Sequential 32-Bit Read Accesses, WSC=2, SRD=1, BCD=0 i.MX50 Applications Processors for Consumer Products, Rev. 4 Freescale Semiconductor WE4 Address V1 WE6 WE8 WE14 WE15 WE13 WE12 WE16 Address V1 WE14 ...
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... In 32-bit muxed address/data (A/D) mode, the 16 MSBs are driven on the data bus. i.MX50 Applications Processors for Consumer Products, Rev Address V1 WE15 WE21 WE20 WE17 WE17 D(V1) D(V2) D(V3) WE16 WE5 WE16 Address V1 WE15 ADVA=1, ADVN=1, and ADH=1 NOTE WE5 WE7 WE9 WE13 D(V4) WE17 Write Data WE7 WE9 WE11 Freescale Semiconductor ...
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... EIM_CSx EIM_ADDR Last Valid Address EIM_RW EIM_LBA EIM_OE EIM_EBx EIM_DATA Figure 25. Asynchronous Memory Read Access i.MX50 Applications Processors for Consumer Products, Rev. 4 Freescale Semiconductor WE5 Address V1 WE15 WE10 Table 43 help to determine timing parameters relative to the chip WE31 Address V1 WE39 WE35 ...
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... WE7 – WE5 – CSN WE8 – WE6 + (WEA – CSA) WE32 Next Address WE34 WE40 WE46 WE42 WE32 Next Address WE40 WE36 WE38 WE44 WE48 Min Max — 3 – CSA — 3 – CSN — (WEA – CSA) Freescale Semiconductor Unit ...
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... DTACK maximum delay from chip input data to internal FF. 4.8 DRAM Timing Parameters This section includes descriptions of the electrical specifications of DRAM MC module which interfaces external DDR2, LPDDR1, and LPDDR2 memory devices. i.MX50 Applications Processors for Consumer Products, Rev. 4 Freescale Semiconductor Determination by Synchronous Measured 1 Parameters WE7 – WE9 + (WEN – CSN) WE10 – ...
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... Address and control output hold time i.MX50 Applications Processors for Consumer Products, Rev DDR4 DDR5 DDR5 bank row Symbol tCK tCH tCL tIS tIH DDR2 DDR3 DDR1 DDR4 DDR5 bank column Min Max Unit 3.75 — ns 0.48 tCK 0.52 tCK ns 0.48 tCK 0.52 tCK ns 0.5 tCK — 0.3 0.5 tCK — 0.3 Freescale Semiconductor ...
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... Address output hold time CK >= 200 MHz DDR6 Address output setup time CK < 200 MHz DDR7 Address output hold time CK < 200 MHz i.MX50 Applications Processors for Consumer Products, Rev. 4 Freescale Semiconductor DDR4 DDR5 rise fall DDR6 DDR7 Symbol tCK tCH ...
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... Figure 30. DRAM Data Output Timing Table 46. DDR Output AC Timing Description DDR12 DDR14 d2 d3 DDR15 DDR16 Symbol Min Max tDQSS -0.3 0.3 tDSH 0.5 tCK 0.5 tCK - 0.3 + 0.3 tDSS 0.5 tCK 0.5 tCK - 0.3 + 0.3 tDQSH 0.48 tCK 0.52 tCK tDQSL 0.48 tCK 0.52 tCK tDS 0.5 tCK — - 1.3 Freescale Semiconductor Unit ...
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... DRAM Data input timing is defined for all DDR types: DDR2, LPDDR1, and LPDDR2. DRAM_SDCLK_B DRAM_SDCLK DRAM_SDQS_B DRAM_SDQS DRAM_D ID DDR20 Positive DQS latching edge to associated CK edge i.MX50 Applications Processors for Consumer Products, Rev. 4 Freescale Semiconductor Table 46. DDR Output AC Timing Description NOTE DDR20 DDR21 d0 Figure 31. DRAM Data Input Timing Table 47. DDR2 Input AC Timing Description ...
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... NOTE Table 48. CSPI Nomenclature and Routing GPIO, KPP, DISP0_DAT, CSI0_DAT, and EIM_D through IOMUX DISP0_DAT, CSI0_DAT, and EIM through IOMUX DISP0_DAT, EIM_A/D, SD1, and SD2 through IOMUX Symbol Min Max tDQSQ — 0.65 tQH 0.45 tCK — -0.85 Table 48. I/O Access Freescale Semiconductor Unit ns ns ...
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... CSPIx_CS_x Lag Time (CS hold time) CS7 CSPIx_DO Setup Time CS8 CSPIx_DO Hold Time CS9 CSPIx_DI Setup Time CS10 CSPIx_DI Hold Time CS11 CSPIx_DRYN Setup Time i.MX50 Applications Processors for Consumer Products, Rev. 4 Freescale Semiconductor Table 49 CS2 CS3 CS2 CS3 Symbol t t RISE/FALL t CSLH ...
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... CS2 CS3 CS2 Symbol t clk RISE/FALL t CSLH t SCS t HCS t Smosi t Hmosi t Smiso t Hmiso CS6 CS5 CS4 Min Max Unit 60 — — ns — — — — — — — — — ns Freescale Semiconductor ...
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... Lag Time (CS hold time) CS7 eCSPIx_DO Setup Time CS8 eCSPIx_DO Hold Time CS9 eCSPIx_DI Setup Time CS10 eCSPIx_DI Hold Time CS11 eCSPIx_DRYN Setup Time i.MX50 Applications Processors for Consumer Products, Rev. 4 Freescale Semiconductor Table 51 CS2 CS3 CS2 CS3 Symbol t t RISE/FALL t CSLH ...
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... SW t RISE/FALL t CSLH t SCS t HCS t Smosi t Hmosi t Smiso t Hmiso lists the eCSPI slave mode timing CS6 CS5 CS4 Min Max 60 — — — — 15 — 5 — 5 — 5 — 5 — 5 — 5 — Freescale Semiconductor Unit ...
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... Clock Frequency (Identification Mode) SD2 Clock Low Time SD3 Clock High Time SD4 Clock Rise Time SD5 Clock Fall Time i.MX50 Applications Processors for Consumer Products, Rev. 4 Freescale Semiconductor Table 53 lists the SD/eMMC4.3 timing characteristics. SD4 SD2 SD5 SCK SD3 CMD SD6 ...
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... Be SCK SD2 DAT0 DAT1 ...... DAT7 SD3 SD4 DAT0 DAT1 ...... DAT7 Figure 37. eMMC4.4 Timing Symbols Card Input Clock f Symbols Min Max t – 2.5 — ISU t 2.5 — IH SD1 SD2 ...... ...... Min Max Unit 0 52 MHz PP Freescale Semiconductor Unit ...
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... M10 FEC_MDC falling edge to FEC_MDIO output invalid (minimum propagation delay) M11 FEC_MDC falling edge to FEC_MDIO output valid (max propagation delay) M12 FEC_MDIO (input) to FEC_MDC rising edge setup M13 FEC_MDIO (input) to FEC_MDC rising edge hold i.MX50 Applications Processors for Consumer Products, Rev. 4 Freescale Semiconductor Symbols t Table 55. RMII Async Inputs Signal Timing M9 Figure 39 56 ...
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... Applications Processors for Consumer Products, Rev Characteristics M14 M12 M13 Table 57 and Figure 40. Table 57. RMII Signal Timing Min Max Unit 40% 60% FEC_MDC period 40% 60% FEC_MDC period M15 M10 M11 Min Max Unit 35% 65% REF_CLK period 35% 65% REF_CLK period 2 — ns — — — ns Freescale Semiconductor ...
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... START IC6 ID Parameter IC1 I2CLK cycle time IC2 Hold time (repeated) START condition IC3 Set-up time for STOP condition i.MX50 Applications Processors for Consumer Products, Rev. 4 Freescale Semiconductor M16 M18 M19 M20 M21 2 C module module timing characteristics. IC11 IC10 ...
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... C-bus specification) One Wire Device Tx “Presence Pulse” OW4 Freescale Semiconductor Unit Max 2 0.9 µs — µs — µs — µs — ns — µs 300 ns 300 ns 400 pF ...
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... Transmission Time Slot — Recovery time Figure 44 depicts Write 1 Sequence timing, lists the timing parameters. One-Wire bus (BATT_LINE) OW7 Figure 44. Write 1 Sequence Timing Diagram i.MX50 Applications Processors for Consumer Products, Rev. 4 Freescale Semiconductor Symbol Min t 480 RSTL t 15 PDH t 60 PDL ...
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... LOW1 t SLOT LOWR t RDV t RELEASE Table 62 lists the PWM timing parameters Figure 46. PWM Timing Min Typ Max 117 120 — — — 15 — 0 — Freescale Semiconductor Unit µs µs µs µs µs µs ...
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... Figure 47 depicts the SJC test clock input timing. Figure 49 depicts the SJC test access port. listed in Table 63. TCK (Input) SJ3 i.MX50 Applications Processors for Consumer Products, Rev. 4 Freescale Semiconductor Table 62. PWM Output Timing Parameter Min 1 12.29 9.91 — — — 8.71 Figure 48 depicts the SJC boundary scan timing. ...
Page 86
... Figure 49. Test Access Port Timing Diagram i.MX50 Applications Processors for Consumer Products, Rev SJ4 Input Data Valid SJ6 Output Data Valid SJ7 SJ6 Output Data Valid SJ8 Input Data Valid SJ10 Output Data Valid SJ11 SJ10 Output Data Valid VIH SJ5 VIH SJ9 Freescale Semiconductor ...
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... SJ12 TRST assert time SJ13 TRST set-up time to TCK low target frequency of SJC mid-point voltage M i.MX50 Applications Processors for Consumer Products, Rev. 4 Freescale Semiconductor SJ13 Figure 50. TRST Timing Diagram Table 63. JTAG Timing 1,2 Parameter Electrical Characteristics All Frequencies ...
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... Applications Processors for Consumer Products, Rev Table 64. Table 64. AUDMUX Port Allocation SSI 1 Internal SSI 2 Internal AUD3 External— AUD3 I/O AUD4 External—EIM or CSPI1 I/O through IOMUX AUD5 External—EIM or SD1 I/O through IOMUX AUD6 External—EIM or DISP2 through IOMUX NOTE Type and Access Freescale Semiconductor ...
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... CK high to FS (wl) high SS12 (Tx) CK high to FS (wl) low SS14 (Tx/Rx) Internal FS rise time SS15 (Tx/Rx) Internal FS fall time SS16 (Tx) CK high to STXD valid from high impedance i.MX50 Applications Processors for Consumer Products, Rev. 4 Freescale Semiconductor Table 65 SS1 SS5 SS4 SS8 SS10 SS14 SS16 SS17 ...
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... For internal frame sync operation using external clock, the FS timing is same as that of Tx Data (for example, during AC97 mode of operation). i.MX50 Applications Processors for Consumer Products, Rev Parameter Synchronous Internal Clock Operation NOTE Min Max Unit — 15.0 ns — 15.0 ns — 6.0 ns 10.0 — ns 0.0 — ns — 25.0 pF Freescale Semiconductor ...
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... SS11 (Rx) CK high to FS (wl) high SS13 (Rx) CK high to FS (wl) low SS20 SRXD setup time before (Rx) CK low SS21 SRXD hold time after (Rx) CK low i.MX50 Applications Processors for Consumer Products, Rev. 4 Freescale Semiconductor Table 66 SS1 SS5 SS4 SS9 SS11 SS20 SS51 ...
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... For internal frame sync operation using external clock, the FS timing is same as that of Tx Data (for example, during AC97 mode of operation). i.MX50 Applications Processors for Consumer Products, Rev Parameter Oversampling Clock Operation NOTE Min Max Unit 15.04 — ns 6.0 — ns — 3.0 ns 6.0 — ns — 3.0 ns Freescale Semiconductor ...
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... SS31 (Tx) CK high to FS (wl) high SS33 (Tx) CK high to FS (wl) low SS37 (Tx) CK high to STXD valid from high impedance SS38 (Tx) CK high to STXD high/low i.MX50 Applications Processors for Consumer Products, Rev. 4 Freescale Semiconductor Table 67 SS22 SS25 SS26 SS27 SS29 SS31 SS37 SS44 ...
Page 94
... For internal frame sync operation using external clock, the FS timing is same as that of Tx Data (for example, during AC97 mode of operation). i.MX50 Applications Processors for Consumer Products, Rev Parameter Synchronous External Clock Operation NOTE Min Max Unit — 15.0 ns 10.0 — ns 2.0 — ns — 6.0 ns Freescale Semiconductor ...
Page 95
... CK high to FS (wl) low SS35 (Tx/Rx) External FS rise time SS36 (Tx/Rx) External FS fall time SS40 SRXD setup time before (Rx) CK low SS41 SRXD hold time after (Rx) CK low i.MX50 Applications Processors for Consumer Products, Rev. 4 Freescale Semiconductor Table 68 SS22 SS26 SS25 SS28 SS30 SS32 SS35 SS40 ...
Page 96
... Applications Processors for Consumer Products, Rev NOTE Table 69. UART I/O Configuration vs. Mode DTE Mode Description Direction DCE Mode Description Input RTS from DTE to DCE Output CTS from DCE to DTE Output Serial data from DCE to DTE Input Serial data from DTE to DCE Freescale Semiconductor ...
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... Baud rate frequency. The maximum baud rate the UART can support is ( ipg_perclk frequency)/16. baud_rate 4.9.10.3 UART IrDA Mode Timing The following sections give the UART transmit and receive timings in IrDA mode. i.MX50 Applications Processors for Consumer Products, Rev. 4 Freescale Semiconductor UA1 Bit 2 Bit 3 Bit 4 ...
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... Possible Parity Bit Max 2 1 baud_rate ref_clk (3/16)*(1 ref_clk baud_rate ref_clk Table 73 UA6 UA5 UA5 Possible Bit 5 Bit 6 Bit 7 Parity Bit Max. ) 1/F + 1/(16*F baud_rate baud_rate baud_rate (5/16)*(1/F ) baud_rate Freescale Semiconductor lists the STOP BIT Units — — lists the STOP BIT Units ) — — ...
Page 99
... USB PHY system clocking parameters Table 76. USB PHY System Clocking Parameters Parameter Conditions Reference Clock deviation frequency 24 MHz Rise/fall time — i.MX50 Applications Processors for Consumer Products, Rev. 4 Freescale Semiconductor Table 74. USB PHY AC Timing Parameters Min Typ 75 — 4 0.5 75 — ...
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... Applications Processors for Consumer Products, Rev. 4 100 Min Typ 0 — 0 — Clock 40 — VBUS Table 77. Comparators Thresholds Conditions Min — 0.8 — 0.8 — 0.2 — 4.4 — 3.0 VBUS = 5.25 V — 7. Max Unit 50 ps 100 Typ Max Unit 1.4 2.0 V 1.4 4.0 V 0.45 0.8 V 4.6 4.75 V — — V μA — 350 Freescale Semiconductor ...
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... Figure 59. 416 MAPBGA 13x13 mm Package Top View Figure 60. 416 MAPBGA 13x13 mm Package Bottom View i.MX50 Applications Processors for Consumer Products, Rev. 4 Freescale Semiconductor Package Information and Contact Assignments Figure 60 shows the bottom view (416 soldier Figure 61 shows the side view of the package ...
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... Figure • Unless otherwise specified dimensions are in millimeters. • All dimensions and tolerances conform to ASME Y14.5M-1994. • Parallelism measurement shall exclude any effect of mark on top surface of package. i.MX50 Applications Processors for Consumer Products, Rev. 4 102 59, Figure 60, and Figure 61: Freescale Semiconductor ...
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... MAPBGA mm, 0.5 mm Pitch Ball Map Table 78 shows the 416 MAPBGA mm, 0.5 mm pitch ball map. Table 78. 416 MAPBGA 13x13 mm, 0.5 mm Pitch Ball Map i.MX50 Applications Processors for Consumer Products, Rev. 4 Freescale Semiconductor Package Information and Contact Assignments 103 ...
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... Package Information and Contact Assignments Table 78. 416 MAPBGA 13x13 mm, 0.5 mm Pitch Ball Map (continued) i.MX50 Applications Processors for Consumer Products, Rev. 4 104 Freescale Semiconductor ...
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... Table 78. 416 MAPBGA 13x13 mm, 0.5 mm Pitch Ball Map (continued) i.MX50 Applications Processors for Consumer Products, Rev. 4 Freescale Semiconductor Package Information and Contact Assignments 105 ...
Page 106
... M10, N10, P10, R10, U10 NVCC_JTAG U9 NVCC_KEYPAD N8 NVCC_LCD U11 NVCC_MISC P8 NVCC_NANDF V9, V10 NVCC_RESET V8 NVCC_SD1 T7 NVCC_SD2 U8 NVCC_SPI R7 i.MX50 Applications Processors for Consumer Products, Rev. 4 106 Ball Number — — — — — — — — — — — — — Comments Freescale Semiconductor ...
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... N15, N17, P11, P12, P13, P14, R11, R12, R13, R14, T17, T18, U12, U13, U14, U15, U16, U17, U18, V17, V18, V20, V21, V23 i.MX50 Applications Processors for Consumer Products, Rev. 4 Freescale Semiconductor Package Information and Contact Assignments — — — ...
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... PoPBGA package, package, and Figure 64 shows the bottom view of the package. Figure 62. 416 PoPBGA Package Top View i.MX50 Applications Processors for Consumer Products, Rev. 4 108 Figure 63 shows the side view of the Freescale Semiconductor ...
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... Figure 63. 416 PoPBGA Package Side View Figure 64. 416 PoPBGA Package Bottom View The following notes apply to Figure • Unless otherwise specified dimensions are in millimeters. i.MX50 Applications Processors for Consumer Products, Rev. 4 Freescale Semiconductor Package Information and Contact Assignments , Figure 63, and Figure 64: ...
Page 110
... Parallelism measurement shall exclude any effect of mark on top surface of package. 5.2.2 416 PoPBGA mm, 0.5 Pitch Ball Map Table 80 shows the 416 PoPBGA ball map. i.MX50 Applications Processors for Consumer Products, Rev. 4 110 Table 80. 416 PoPBGA Ball Map Freescale Semiconductor ...
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... Table 80. 416 PoPBGA Ball Map (continued) i.MX50 Applications Processors for Consumer Products, Rev. 4 Freescale Semiconductor Package Information and Contact Assignments 111 ...
Page 112
... Package Information and Contact Assignments Table 80. 416 PoPBGA Ball Map (continued) i.MX50 Applications Processors for Consumer Products, Rev. 4 112 Freescale Semiconductor ...
Page 113
... NVCC_JTAG U9 NVCC_KEYPAD N8 NVCC_LCD U11 NVCC_MISC P8 NVCC_NANDF V9, V10 i.MX50 Applications Processors for Consumer Products, Rev. 4 Freescale Semiconductor Package Information and Contact Assignments Ball Number — — These are the 1.2V supply to both the i.MX50 DRAM controller as well as the PoP LPDDR2. — — — ...
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... V I/O for the PoP eMMC NAND. Note that on the PoPBGA package, USB_OTG_VDDA25 and USB_H1_VDDA25 are shorted together. Note that on the PoPBGA package, USB_OTG_VDDA33 and USB_H1_VDDA33 are shorted together. — — — — — Freescale Semiconductor ...
Page 115
... This section contains the outline drawing, signal assignment map, ground, power, reference ID (by ball grid location) for the mm, 0.8 mm pitch, 400 pin MAPBGA package. i.MX50 Applications Processors for Consumer Products, Rev. 4 Freescale Semiconductor Package Information and Contact Assignments — — ...
Page 116
... Figure 67 shows the side view of the package. A1 INDEX AREA Figure 65. 400 MAPBGA 17x17 mm Package Top view i.MX50 Applications Processors for Consumer Products, Rev. 4 116 Figure 66 shows the bottom view of the Top View C 17 0.15 Freescale Semiconductor ...
Page 117
... Figure 66. 400 MAPBGA 17x17 mm Package Bottom View i.MX50 Applications Processors for Consumer Products, Rev. 4 Freescale Semiconductor Package Information and Contact Assignments 117 ...
Page 118
... Parallelism measurement shall exclude any effect of mark on top surface of package. 5.3.2 400 MAPBGA Ball Map Table 82 shows the 400 MAPBGA ball map. Table 82. 400 MAPBGA Ball Map i.MX50 Applications Processors for Consumer Products, Rev. 4 118 65, Figure 66, and Figure 67: Freescale Semiconductor ...
Page 119
... Table 82. 400 MAPBGA Ball Map (continued) i.MX50 Applications Processors for Consumer Products, Rev. 4 Freescale Semiconductor Package Information and Contact Assignments 119 ...
Page 120
... Package Information and Contact Assignments Table 82. 400 MAPBGA Ball Map (continued) i.MX50 Applications Processors for Consumer Products, Rev. 4 120 Freescale Semiconductor ...
Page 121
... Table 82. 400 MAPBGA Ball Map (continued) i.MX50 Applications Processors for Consumer Products, Rev. 4 Freescale Semiconductor Package Information and Contact Assignments 121 ...
Page 122
... N10 R10 G11 H11 N11 R11 G12 H12 M12 N12 R12 G13 H13 J13 K13 L13 M13 N13 P13 R13 G14 H14 J14 L14 M14 P14 R14 H15 M15 R15 i.MX50 Applications Processors for Consumer Products, Rev. 4 122 Ball Number Freescale Semiconductor ...
Page 123
... DISP_D14 V15 AB23 DISP_D15 V16 AD21 DISP_D2 AA13 AD15 DISP_D3 Y13 AC15 DISP_D4 AA14 AC24 DISP_D5 Y14 AB24 i.MX50 Applications Processors for Consumer Products, Rev. 4 Freescale Semiconductor 400 MAPBGA Pin Power Ball Domain Number V3 NVCC_RESET U3 NVCC_RESET T10 USB_H1_VDDA25, USB_H1_VDDA33 V4 NVCC_JTAG Y4 NVCC_SRTC K4 ...
Page 124
... ALT0 OUT-LO DRAMCALI — — B DRAM ALT0 OUT-HI DRAM ALT0 OUT-HI DRAM ALT0 OUT-HI DRAM ALT0 IN DRAM ALT0 IN Freescale Semiconductor IOMUX After Reset Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper — ...
Page 125
... U18 DRAM_D6 T23 T18 DRAM_D7 U24 R18 DRAM_D8 J23 J18 DRAM_D9 H24 H20 i.MX50 Applications Processors for Consumer Products, Rev. 4 Freescale Semiconductor Package Information and Contact Assignments 400 MAPBGA Pin Power Pad Type Ball Domain Number E17 NVCC_EMI_DRAM DRAM D19 NVCC_EMI_DRAM ...
Page 126
... ALT0 IN DRAMCLK ALT0 IN DRAMCLK ALT0 IN DRAMCLK ALT0 IN DRAM ALT0 OUT-HI ANALOG — — HVIO ALT1 IN HVIO ALT1 IN Freescale Semiconductor IOMUX After Reset Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper — Keeper — Keeper Keeper — — ...
Page 127
... B22 EIM_DA6 D8 B18 EIM_DA7 E8 B17 EIM_DA8 A7 A18 EIM_DA9 B7 A17 EIM_EB0 A4 D15 EIM_EB1 B4 D14 EIM_LBA E5 B13 i.MX50 Applications Processors for Consumer Products, Rev. 4 Freescale Semiconductor 400 MAPBGA Pin Power Ball Domain Number N2 NVCC_SPI L4 N3 NVCC_SPI L2 L4 NVCC_SPI N1 NVCC_SPI L1 N4 NVCC_SPI M2 NVCC_SPI A5 NVCC_EIM ...
Page 128
... HVIO ALT1 IN Keeper HVIO ALT1 IN Keeper HVIO ALT1 IN Keeper HVIO ALT1 IN Keeper HVIO ALT1 IN Keeper HVIO ALT1 IN Keeper HVIO ALT1 IN Keeper HVIO ALT1 IN Keeper HVIO ALT1 IN Keeper HVIO ALT1 IN Keeper HVIO ALT1 IN Keeper HVIO ALT1 IN Keeper HVIO ALT1 IN Keeper Freescale Semiconductor ...
Page 129
... I2C2_SDA F2 B6 I2C3_SCL G1 A4 I2C3_SDA G2 B5 JTAG_MOD V7 V5 JTAG_TCK W4 W4 i.MX50 Applications Processors for Consumer Products, Rev. 4 Freescale Semiconductor Package Information and Contact Assignments 400 MAPBGA Pin Power Pad Type Ball Domain Number E12 NVCC_EPDC F15 NVCC_EPDC C12 NVCC_EPDC B12 NVCC_EPDC ...
Page 130
... ALT0 IN 100K PU HVIO ALT1 IN Keeper HVIO ALT1 IN Keeper HVIO ALT1 IN Keeper HVIO ALT1 IN Keeper HVIO ALT1 IN Keeper HVIO ALT1 IN Keeper HVIO ALT1 IN Keeper HVIO ALT1 IN Keeper HVIO ALT1 IN Keeper HVIO ALT1 IN Keeper HVIO ALT1 IN Keeper Freescale Semiconductor After Reset — — ...
Page 131
... AD14 SSI_TXFS H4 AC12 TEST_MODE AC2 AC2 UART1_CTS H2 B4 UART1_RTS J2 B3 UART1_RXD J1 A2 UART1_TXD H1 A3 UART2_CTS K2 B2 i.MX50 Applications Processors for Consumer Products, Rev. 4 Freescale Semiconductor 400 MAPBGA Pin Power Ball Domain Number W2 NVCC_SD2 T4 NVCC_SD2 V2 NVCC_SD2 U2 NVCC_SD2 R4 NVCC_SD2 W1 NVCC_SD2 T2 NVCC_SD2 Y14 NVCC_NANDF ...
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... HVIO ALT1 IN — — — — Freescale Semiconductor ...
Page 133
... Freescale Semiconductor Substantive Change(s) 7, added new part number information for MCIMX507CVK8B. 66, updated timing of EIM_DTACK. 24: 7, added the following new part numbers: MCIMX508CZK8B, 7, added a new column, T junction 8, added a new row for 416 PoPBGA package. by removing “LDOx3” and “DC-DC 1.2V.” 17, updated details for the following signals: ...
Page 134
... Supply column, changed CHRG_DET_B to CHGR_DET_B. for 416 MAPBGA, DRAM_SDCLK_0 pin number for 416 MAPBGA, DRAM_SDCLK_1 pin number for 416 MAPBGA, DRAM_SDQS0 pin number was changed pad type of pin DRAM_CALIBRATION to changed pad type of pins DRAM_SDCLK_0, Freescale Semiconductor ...
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... Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. All other product or service names are the property of their respective owners. ARM is the registered trademark of ARM Limited. ARM ...