MCIMX508CZK8B Freescale Semiconductor, MCIMX508CZK8B Datasheet - Page 78

• Manufacturer Part Number: MCIMX508CZK8B
• Description: Processors - Application Specialized CODEX REV 1.1
• Manufacturer: Freescale Semiconductor
• Type: Multimedia Applicationsr

Specifications of MCIMX508CZK8B

• Core: ARM Cortex A8
• Processor Series: i.MX50

Electrical Characteristics
4.9.3.2
Figure 37
aware that only DAT0-7 is sampled on both edges of clock (not applicable to CMD).
78
1
2
3
4
To satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns.
SD6
SD7
SD8
In low speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V.
In normal (full) speed mode for SD/SDIO card, clock frequency can be any value between 0–25 MHz. In high-speed mode,
clock frequency can be any value between 0–50 MHz.
In normal (full) speed mode for MMC card, clock frequency can be any value between 0–20 MHz. In high-speed mode, clock
frequency can be any value between 0–52 MHz.
ID
SD1
ID
eSDHC Output Delay
eSDHC Input Setup Time
eSDHC Input Hold Time
output from eSDHCv3 to card
input from card to eSDHCv3
depicts the timing of eMMC4.4, and
eMMC4.4 (Dual Data Rate) eSDHCv3 and uSDHC AC Timing
Clock Frequency (MMC Full Speed/High Speed)
Table 53. SD/eMMC4.3 Interface Timing Specification (continued)
i.MX50 Applications Processors for Consumer Products, Rev. 4
eSDHC Output/Card Inputs CMD, DAT (Reference to CLK)
eSDHC Input/Card Outputs CMD, DAT (Reference to CLK)
eSDHC Output/Card Inputs CMD, DAT (Reference to CLK)
Table 54. eMMC4.4 Interface Timing Specification
4
Parameter
Parameter
DAT0
......
DAT7
DAT1
DAT0
......
DAT7
SCK
DAT1
Figure 37. eMMC4.4 Timing
Card Input Clock
SD2
Table 54
SD3
lists the eMMC4.4 timing characteristics. Be
Symbols
SD4
f
Symbols
PP
t
t
ISU
t
OD
IH
SD2
SD1
Min
0
Min
2.5
2.5
–2
Max
52
Freescale Semiconductor
Max
......
—
—
2
......
MHz
Unit
Unit
ns
ns
ns