MCIMX508CZK8B Freescale Semiconductor, MCIMX508CZK8B Datasheet - Page 19

• Manufacturer Part Number: MCIMX508CZK8B
• Description: Processors - Application Specialized CODEX REV 1.1
• Manufacturer: Freescale Semiconductor
• Type: Multimedia Applicationsr

Specifications of MCIMX508CZK8B

• Core: ARM Cortex A8
• Processor Series: i.MX50

Freescale Semiconductor
PMIC_RDY
POP_EMMC_RST
(416 PoPBGA Only)
POP_LPDDR2_ZQ0/ZQ1
(416 PoPBGA Only)
POP_LPDDR2_1.8V
(416 PoPBGA Only)
POP_NAND_VCC
(416 PoPBGA Only)
POR_B
RESET_IN_B
SSI_EXT1_CLK,
SSI_EXT2_CLK
TEST_MODE
USB_H1_GPANAIO,
USB_OTG_GPANAIO
USB_H1_RREFEXT,
USB_OTG_RREFEXT
Signal Name
i.MX50 Applications Processors for Consumer Products, Rev. 4
Table 5. Special Signal Considerations (continued)
This input may be used by a PMIC to signal to the i.MX50 that the PMIC supply outputs are at
operating levels when resuming from STOP mode. The PMIC_RDY input is pin muxed on ALT3
of the I2C3_SCL pin and is in the NVCC_MISC domain.
This pin is the PoP eMMC 4.4 Reset pin. The customer may connect this on their PCB to any
free GPIO, or just leave floating for non-4.4 eMMC. This pin does not connect to the i.MX50 die.
These pins connect to the PoP LPDDR2 DRAM ZQ pins and should be connected on the
customer PCB to a 240 Ω 1% resistor to ground if used. These pins do not connect to the
i.MX50 die.
These pins are the 1.8 V supply for the PoP LPDDR2 DRAM. These pins do not connect to the
i.MX50 die.
This is the 3.3V I/O and memory supply for the PoP eMMC. Note that most eMMC can operate
with a 1.8V I/O or a 3.3V I/O voltage. However, because we tied the eMMC memory and I/O
domains together, you can't use the 1.8 V I/O option for the PoP eMMC, only 3.3 V I/O.
This POWER-ON RESET input is a cold reset negative logic input that resets all modules and
logic in the IC. The POR_B pin should have an external 68 K pull-up to NVCC_RESET and a
1 μF capacitor to ground.
Note: The POR_B input must be immediately asserted at power-up and remain asserted until
after the last power rail is at its working voltage.
This warm reset negative logic input resets all modules and logic except for the following:
The SSI_EXT1_CLK and SSI_EXT2_CLK outputs are recommended for generating a clock
output from the i.MX50. Use of the CKO1 and CKO2 clock outputs is not recommended, as the
large number of combinational logic muxes on those signals will impact jitter and duty-cycle.
Note that these two clock outputs do not have dedicated pins: SSI_EXT1_CLK is IOMUX ALT3
on the OWIRE pin, and SSI_EXT2_CLK is IOMUX ALT3 of the EPITO pin.
TEST_MODE is for Freescale factory use only. This signal is internally connected to an on-chip
pull-down device. The user must either float this signal or tie it to GND.
These signals are reserved for Freescale manufacturing use only. Users should float these
outputs.
These signals determine the reference current for the USB PHY bandgap reference. An
external 6.04 kΩ 1% resistor to GND is required. This resistor should be connected through a
short (low impedance connection) and placed away from other noisy regions.
If USB_H1 is not used, the H1 RREFEXT resistor may be eliminated and the pin left floating.
If USB_OTG is not used, the OTG RREFEXT resistor may be eliminated and the pin left
floating.
• Test logic (JTAG, IOMUXC, DAP)
• SRTC
• Cold reset logic of WDOG—Some WDOG logic is only reset by POR_B. See WDOG
chapter in the MCIMX50 Applications Processor Reference Manual (MCIMX50RM) for
details.
Remarks
Modules List
19