IDT70V9269S12PRFI IDT, Integrated Device Technology Inc, IDT70V9269S12PRFI Datasheet
IDT70V9269S12PRFI
Specifications of IDT70V9269S12PRFI
800-1399
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IDT70V9269S12PRFI Summary of contents
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... Features: True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed clock to data access – Commercial: 6.5/7.5/9/12/15ns (max.) – Industrial: 7.5ns (max.) Low-power operation – IDT70V9279/69S Active: 429mW (typ.) Standby: 3.3mW (typ.) – IDT70V9279/69L Active: 429mW (typ.) Standby: 1.32mW (typ.) ...
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... High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM Description: The IDT70V9279/ high-speed 32/16K x 16 bit synchronous Dual-Port RAM. The memory array utilizes Dual-Port memory cells to allow simultaneous access of any address from both ports. Registers on control, data, and address inputs provide minimal setup and hold times. ...
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IDT70V9279/69S/L High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM Pin Names Left Port Right Port CE CE Chip Enables CE CE 0L, 1L 0R, 1R R/W R/W Read/Write Enable Output Enable L R (1) (1) A ...
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IDT70V9279/69S/L High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM Truth Table II—Address Counter Control Previous Internal External Internal Address Address Address Used CLK ↑ ↑ ↑ ...
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IDT70V9279/69S/L High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol Parameter ( Input Leakage Current Output Leakage Current LO V Output Low Voltage OL ...
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IDT70V9279/69S/L High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM DC Electrical Characteristics Over the Operating Temperature Supply Voltage Range Symbol Parameter Test Condition I Dynamic CE and Operating Outputs Disabled, (1) Current (Both MAX ...
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IDT70V9279/69S/L High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM AC Test Conditions Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load DATA OUT 435Ω Figure 1. AC Output Test load. , tCD 1 tCD ...
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IDT70V9279/69S/L High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM AC Electrical Characteristics Over the Operating Temperature Range (Read and Write Cycle Timing) Symbol t Clock Cycle Time (Flow-Through) CYC1 (2) t Clock Cycle Time (Pipelined) CYC2 t Clock High Time ...
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IDT70V9279/69S/L High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM AC Electrical Characteristics Over the Operating Temperature Range (Read and Write Cycle Timing) Symbol t Clock Cycle Time (Flow-Through) CYC1 t Clock Cycle Time (Pipelined) CYC2 t Clock High Time (Flow-Through) ...
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IDT70V9279/69S/L High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM Timing Waveform of Read Cycle for Flow-through Output (3,7) (FT/PIPE = V ) "X" CH1 CLK UB, ...
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IDT70V9279/69S/L High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM Timing Waveform of a Bank Select Pipelined Read t CYC2 t CH2 CLK ADDRESS (B1 0(B1) DATA OUT(B1 ...
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IDT70V9279/69S/L High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM Timing Waveform with Port-to-Port Flow-Through Read CLK "A" R/W "A" ADDRESS "A" MATCH t SD DATA IN "A" VALID CLK "B" R/W "B" ADDRESS "B" DATA OUT ...
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... Output state (High, Low, or High-impedance) is determined by the previous cycle control signals UB, LB, and ADS = V , CNTEN, and CNTRST = Addresses do not have to be accessed sequentially since ADS = V reference use only. 5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity. t CL2 ...
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... Output state (High, Low, or High-impedance) is determined by the previous cycle control signals UB, LB, and ADS = V , CNTEN, and CNTRST = Addresses do not have to be accessed sequentially since ADS = V reference use only. 5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity. t CL1 ...
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IDT70V9279/69S/L High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM Timing Waveform of Pipelined Read with Address Counter Advance t CYC2 t t CH2 CL2 CLK ADDRESS t t SAD HAD ADS CNTEN ( ...
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IDT70V9279/69S/L High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM Timing Waveform of Write with Address Counter Advance (Flow-Through or Pipelined Outputs) t CYC2 t CH2 CLK ADDRESS (3) INTERNAL An ADDRESS t t SAD HAD ...
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... LOW to HIGH transition of the clock signal. An asynchronous output enable is provided to ease asynchronous bus interfacing. Counter enable inputs are also provided to staff the operation of the address counters for fast interleaved memory applications. A HIGH LOW on CE for one clock cycle will power down ...
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IDT70V9279/69S/L High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM Ordering Information XXXXX Device Power Speed Package Type NOTE: 1. Contact your local sales office for industrial temp. range for other speeds, packages and powers. 2. Green parts ...
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IDT70V9279/69S/L High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM Datasheet Document History 01/12/99: Initiated datasheet document history Converted to new format Cosmetic and typographical corrections Added additional notes to pin configurations Page 14 Added Depth & Width Expansion section 06/15/99: ...