AD6643-250EBZ Analog Devices, AD6643-250EBZ Datasheet - Page 11

• Manufacturer Part Number: AD6643-250EBZ
• Description: Data Conversion IC Development Tools 11 Bit Dual IF Diversity 3G Receiver
• Manufacturer: Analog Devices
• Type: ADCr
• Series: AD6643r

Specifications of AD6643-250EBZ

• Rohs: yes
• Product: Evaluation Boards
• Tool Is For Evaluation Of: AD6643-250
• Interface Type: SPI, USB
• Operating Supply Voltage: 6 V
• Description/function: 250 MSPs per channel dual IF receiver
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Current: 2 A
• Factory Pack Quantity: 1
• For Use With: HSC-ADC-EVALCZ

Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Table 8. Pin Function Descriptions for the Interleaved Parallel LVDS Mode
Pin No.
ADC Power Supplies
ADC Analog
Digital Input
Digital Outputs
10, 19, 28, 37
49, 50, 53, 54, 59, 60, 63, 64
4 to 9, 11 to 14, 55, 56, 58
0
51
52
62
61
57
1
2
3
15
16
18
17
21
20
23
22
27
Mnemonic
DRVDD
AVDD
DNC
AGND,
Exposed
Paddle
VIN+A
VIN−A
VIN+B
VIN−B
VCM
CLK+
CLK−
SYNC
D0− (LSB)
D0+ (LSB)
D1+
D1−
D2+
D2−
D3+
D3−
D4+
INDICATOR
D0– (LSB)
D0+ (LSB)
NOTES
1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.
2. THE EXPOSED THERMAL PADDLE ON THE BOTTOM OF THE PACKAGE
PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED PADDLE
MUST BE CONNECTED TO GROUND FOR PROPER OPERATION.
DRVDD
Figure 4. Pin Configuration (Top View), LFCSP Interleaved Parallel LVDS
SYNC
CLK+
CLK–
PIN 1
DNC
DNC
DNC
DNC
DNC
DNC
DNC
DNC
DNC
DNC
10
12
13
14
15
16
11
1
2
3
4
5
6
7
8
9
Type
Supply
Supply
Ground
Input
Input
Input
Input
Output
Input
Input
Input
Output
Output
Output
Output
Output
Output
Output
Output
Output
Rev. C | Page 11 of 40
INTERLEAVED
(Not to Scale)
PARALLEL
AD6643
TOP VIEW
Description
Digital Output Driver Supply (1.8 V Nominal).
Analog Power Supply (1.8 V Nominal).
Do Not Connect. Do not connect to these pins.
Analog Ground. The exposed thermal paddle on the bottom of the
package provides the analog ground for the device. This exposed paddle
must be connected to ground for proper operation.
Differential Analog Input Pin (+) for Channel A.
Differential Analog Input Pin (−) for Channel A.
Differential Analog Input Pin (+) for Channel B.
Differential Analog Input Pin (−) for Channel B.
Common-Mode Level Bias Output for Analog Inputs. This pin should be
decoupled to ground using a 0.1 μF capacitor.
ADC Clock Input—True.
ADC Clock Input—Complement.
Digital Synchronization Pin. Slave mode only.
Channel A/Channel B LVDS Output Data 0—True.
Channel A/Channel B LVDS Output Data 0—Complement.
Channel A/Channel B LVDS Output Data 1—True.
Channel A/Channel B LVDS Output Data 1—Complement.
Channel A/Channel B LVDS Output Data 2—True.
Channel A/Channel B LVDS Output Data 2—Complement.
Channel A/Channel B LVDS Output Data 3—True.
Channel A/Channel B LVDS Output Data 3—Complement.
Channel A/Channel B LVDS Output Data 4—True.
LVDS
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PDWN
OEB
CSB
SCLK
SDIO
OR+
OR–
D10+ (MSB)
D10– (MSB)
D9+
D9–
DRVDD
D8+
D8–
D7+
D7–
AD6643