AD6643-250EBZ Analog Devices, AD6643-250EBZ Datasheet - Page 35

• Manufacturer Part Number: AD6643-250EBZ
• Description: Data Conversion IC Development Tools 11 Bit Dual IF Diversity 3G Receiver
• Manufacturer: Analog Devices
• Type: ADCr
• Series: AD6643r

Specifications of AD6643-250EBZ

• Rohs: yes
• Product: Evaluation Boards
• Tool Is For Evaluation Of: AD6643-250
• Interface Type: SPI, USB
• Operating Supply Voltage: 6 V
• Description/function: 250 MSPs per channel dual IF receiver
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Current: 2 A
• Factory Pack Quantity: 1
• For Use With: HSC-ADC-EVALCZ

Data Sheet
MEMORY MAP REGISTER DESCRIPTION
For more information on functions controlled in Register 0x00
to Register 0x20, see the
to High Speed ADCs via SPI, available at www.analog.com.
Sync Control (Register 0x3A)
Bits[7:3]—Reserved
Bit 2—Clock Divider Next Sync Only
If the master sync enable buffer bit (Address 0x3A, Bit0) and
the clock divider sync enable bit (Address 0x3A, Bit 1) are high,
Bit 2 allows the clock divider to sync to the first sync pulse it
receives and to ignore the rest. The clock divider sync enable bit
(Address 0x3A, Bit 1) resets after it syncs.
Bit 1—Clock Divider Sync Enable
Bit 1 gates the sync pulse to the clock divider. The sync signal is
enabled when Bit 1 is high and Bit 0 is high. This is continuous
sync mode.
Bit 0—Master Sync Buffer Enable
Bit 0 must be set high to enable any of the sync functions. If the
sync capability is not used this bit should remain low to
conserve power.
AN-877
Application Note, Interfacing
Rev. C | Page 35 of 40
NSR Control (Register 0x3C)
Bits[7:4]—Reserved
Bits[3:1]—NSR Mode
Bits[3:1] determine the bandwidth mode of the NSR. When
Bits[3:1] are set to 000, the NSR is configured for a 22% BW
mode that provides enhanced SNR performance over 22% of
the sample rate. When Bits[3:1] are set to 001, the NSR is con-
figured for a 33% BW mode that provides enhanced SNR
performance over 33% of the sample rate.
Bit 0—NSR Enable
The NSR is enabled when Bit 0 is high and disabled when Bit 0
is low.
NSR Tuning Word (Register 0x3E)
Bits[7:6]—Reserved
Bits[5:0]—NSR Tuning Word
The NSR tuning word sets the band edges of the NSR band. In
22% BW mode, there are 57 possible tuning words; in 33% BW
mode, there are 34 possible tuning words. For either mode, each
step represents 0.5% of the ADC sample rate. For the equations
that are used to calculate the tuning word based on the BW
mode of operation, see the Noise Shaping Requantizer (NSR)
section.
AD6643