M58BW16FB4T3F NUMONYX, M58BW16FB4T3F Datasheet - Page 20

• Manufacturer Part Number: M58BW16FB4T3F
• Description: IC FLASH 16MBIT 45NS 80PQFP
• Manufacturer: NUMONYX

Specifications of M58BW16FB4T3F

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 16M (512K x 32)
• Speed: 45ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 80-MQFP, 80-PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: M58BW16FB4T3FCT

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Signal descriptions
See
connected to this device.
Address inputs (A0-Amax)
Amax is equal to A18 in the M58BW16F, and to A19 in the M58BW32F.
The Address inputs are used to select the cells to access in the memory array during Bus
operations. During Bus Write operations they control the commands sent to the command
interface of the Program/Erase controller. Chip Enable must be Low when selecting the
addresses.
The Address inputs are latched on the rising edge of Latch Enable L or Burst Clock K,
whichever occurs first, in a Read operation. The Address inputs are latched on the rising
edge of Chip Enable, Write Enable or Latch Enable, whichever occurs first in a Write
operation. The address latch is transparent when Latch Enable is Low, V
internally latched in an Erase or Program operation.
Data inputs/outputs (DQ0-DQ31)
The Data inputs/outputs output the data stored at the selected address during a Bus Read
operation, or are used to input the data during a program operation. During Bus Write
operations they represent the commands sent to the command interface of the
Program/Erase controller. When used to input data or Write commands they are latched on
the rising edge of Write Enable or Chip Enable, whichever occurs first.
When Chip Enable and Output Enable are both Low, V
data bus outputs data from the memory array, the Electronic Signature, the Block Protection
Configuration Register, the CFI information or the contents of Burst Configuration Register
or Status Register. The data bus is high impedance when the device is deselected with Chip
Enable at V
Status Register content is output on DQ0-DQ7 and DQ8-DQ31 are at V
Chip Enable (E)
The Chip Enable, E, input activates the memory control logic, input buffers, decoders and
sense amplifiers. Chip Enable, E, at V
consumption to the standby level.
Output Enable (G)
The Output Enable, G, gates the outputs through the data output buffers during a Read
operation, when Output Disable GD is at V
are high impedance independently of Output Disable.
Figure 1: Logic diagram
IH
, Output Enable at V
and
Table 1: Signal
IH
, Output Disable at V
IH
deselects the memory and reduces the power
IH
. When Output Enable G is at V
names, for a brief overview of the signals
IL
IL
, and Output Disable is at V
or Reset/Power-down at V
IL
IL
.
. The address is
IH
, the outputs
IH,
IL
. The
the