M58BW16FB4T3F NUMONYX, M58BW16FB4T3F Datasheet - Page 28

• Manufacturer Part Number: M58BW16FB4T3F
• Description: IC FLASH 16MBIT 45NS 80PQFP
• Manufacturer: NUMONYX

Specifications of M58BW16FB4T3F

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 16M (512K x 32)
• Speed: 45ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 80-MQFP, 80-PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: M58BW16FB4T3FCT

3.2.2
3.3
3.3.1
3.3.2
28/87
Synchronous Burst Read Suspend
During a Synchronous Burst Read operation it is possible to suspend the operation, freeing
the data bus for other higher priority devices.
A valid Synchronous Burst Read operation is suspended when both Output Enable and
Burst Address Advance are High, V
the Burst counter and the Output Enable going High, V
Synchronous Burst Read operation can be resumed by setting Output Enable Low.
Table 7.
1. X = Don't care, V
2. M15 = 0, Bit M15 is in the Burst Configuration Register.
3. R = Rising edge.
Burst Configuration Register
The Burst Configuration Register is used to configure the type of bus access that the
memory will perform.
The Burst Configuration Register is set through the command interface and will retain its
information until it is re-configured, the device is reset, or the device goes into Reset/Power-
down mode. The Burst Configuration Register bits are described in
the selection of the Burst length, Burst type, Burst X and Y latencies and the Read
operation. Refer to
Read Select bit (M15)
The Read Select bit, M15, is used to switch between Asynchronous and Synchronous Bus
Read operations. When the Read Select bit is set to ’1’, Bus Read operations are
asynchronous; when the Read Select bit is set to ’0’, Bus Read operations are synchronous.
On reset or power-up the Read Select bit is set to’1’ for asynchronous accesses.
Standby Disable bit (M14)
The Standby Disable bit, M14, is used to disable the Standby mode. When the Standby bit is
‘1’, the device will not enter Standby mode when Chip Enable goes High, V
Synchronous
Burst Read
Bus operation
(2)
Synchronous Burst Read Bus operations
Address Latch
Read
Read Suspend
Read Resume
Burst Address
Advance
Read Abort, E
Read Abort, RP
IL
or V
Figure 4
IH
Step
.
for examples of Synchronous Burst configurations.
IH
V
V
V
V
V
V
. The Burst Address Advance going High, V
E
X
IH
IL
IL
IL
IL
IL
V
V
V
V
V
G
X
X
IH
IH
IH
IL
IL
GD
V
V
X
X
X
X
X
IH
IH
RP
V
V
V
V
V
V
V
IH
IH
IH
IH
IH
IH
IH
IL
, inhibits the data outputs. The
(1)
R
R
R
R
K
X
X
X
(3)
(3)
(3)
(3)
V
V
V
V
V
X
X
L
IH
IH
IH
IH
IL
Table
V
V
V
V
B
X
X
X
IH
IL
IL
IL
8. They specify
IH
.
Address input
Data output
Data output
DQ0-DQ31
A0-Amax
High Z
High Z
High Z
High Z
IH
, stops