M58BW16FB4T3F NUMONYX, M58BW16FB4T3F Datasheet - Page 24

• Manufacturer Part Number: M58BW16FB4T3F
• Description: IC FLASH 16MBIT 45NS 80PQFP
• Manufacturer: NUMONYX

Specifications of M58BW16FB4T3F

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 16M (512K x 32)
• Speed: 45ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 80-MQFP, 80-PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: M58BW16FB4T3FCT

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3.1
3.1.1
3.1.2
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Bus operations
Each bus operations that controls the memory is described in this section, see tables
7
Configuration Register; the bits in this register are described at the end of this section.
On power-up or after a hardware reset the memory defaults to Asynchronous Bus Read and
Asynchronous Bus Write. No synchronous operation can be performed until the Burst
Control Register has been configured.
The Electronic Signature, Block Protection Configuration, CFI or Status Register will be read
in asynchronous mode regardless of the Burst Control Register settings.
Typically glitches of less than 5 ns on Chip Enable or Write Enable are ignored by the
memory and do not affect bus operations.
Asynchronous Bus operations
For asynchronous bus operations refer to
access will start at whichever of the three following events occurs last: valid address
transition, Chip Enable, E, going Low, V
Asynchronous Bus Read
Asynchronous Bus Read operations read from the memory cells, or specific registers
(Electronic Signature, Block Protection Configuration Register, Status Register, CFI and
Burst Configuration Register) in the command interface. A valid bus operation involves
setting the desired address on the Address inputs, applying a Low signal, V
Enable and Output Enable and keeping Write Enable and Output Disable High, V
Data inputs/outputs will output the value, see
waveforms, and
the output becomes valid.
Asynchronous Read is the default read mode which the device enters on power-up or on
return from Reset/Power-down.
Asynchronous Latch Controlled Bus Read
Asynchronous Latch Controlled Bus Read operations read from the memory cells or specific
registers in the command interface. The address is latched in the memory before the value
is output on the data bus, allowing the address to change during the cycle without affecting
the address that the memory uses.
A valid bus operation involves setting the desired address on the Address inputs, setting
Chip Enable and Latch Enable Low, V
latched on the rising edge of Latch Enable. Once latched, the Address inputs can change.
Set Output Enable Low, V
Asynchronous Latch Controlled Bus Read AC waveforms
Read AC
Note that, since the Latch Enable input is transparent when set Low, V
Read operations can be performed when the memory is configured for Asynchronous Latch
Enable bus operations by holding Latch Enable Low, V
Bus operations, for a summary. The bus operation is selected through the Burst
characteristics, for details on when the output becomes valid.
Table 19: Asynchronous Bus Read AC
IL
, to read the data on the Data inputs/outputs; see
IL
IL
and keeping Write Enable High, V
or Latch Enable, L, going Low, V
Table 6
Figure 7: Asynchronous Bus Read AC
together with the following text. The read
IL
characteristics, for details of when
throughout the bus operation.
and
Table 19: Asynchronous Bus
IL
, Asynchronous Bus
IH
IL
IL
; the address is
.
, to Chip
Figure 8:
IH
. The
6
and